summaryrefslogtreecommitdiffstats
path: root/sys/powerpc
Commit message (Collapse)AuthorAgeFilesLines
* Fix compilation in the case when kernel doesn't have KDB ebabled.sobomax2008-10-301-0/+7
| | | | subr_kdb.c still references breakpoint() in this case.
* Fix some possible infinite loops in the ADB code, and remove some hacksnwhitehorn2008-10-302-21/+9
| | | | | that were inserted in desperation during bring-up. In addition, move ADB bus enumeration and child attachment to when interrupts are available.
* Add support for little-endian compilations to this file.marcel2008-10-301-1/+15
|
* DBDMA can transfer a maximum of 64K - 1 bytes per descriptor, as the bytenwhitehorn2008-10-281-0/+6
| | | | | | count field is 16 bits. Inform ATA of this fact. Reported by: Marco Trillo
* Clean up some magic numbers in the DBDMA code by replacing them withnwhitehorn2008-10-272-11/+20
| | | | | | appropriately defined constants. Suggested by: gnn
* Add support for kernel profiling for both AIM and BookE.marcel2008-10-273-51/+83
| | | | Obtained from: Juniper Networks, Inc (BookE support).
* Remove unused declarations (interrupt_vector_{base|top}).marcel2008-10-271-3/+0
|
* Declare btext and etext. Needed by sys/kern/subr_prof.c formarcel2008-10-271-0/+3
| | | | for kernel profiling.
* Bring Kauai ATA driver in line with Macio ATA by reading the PIO config regnwhitehorn2008-10-271-6/+2
| | | | | | | | | | | | to set the initial PIO mode instead of assuming PIO4. There are still a few nagging issues: - There are some problems with 64 K DMA transfers waiting on lower level changes. - ATAPI DMA is broken on Marcel's Mac Mini because we need an ATA SELECT hook propagated up to individual drivers for hardware without timing registers for each ATA channel.
* Add ADB support. This provides support for the external ADB bus on the PowerMacnwhitehorn2008-10-269-0/+1966
| | | | | | | | G3 as well as the internal ADB keyboard and mice in PowerBooks and iBooks. This also brings in Mac GPIO support, for which we should eventually have a better interface. Obtained from: NetBSD (CUDA and PMU drivers)
* Enable the cfi(4) driver.marcel2008-10-251-0/+1
|
* Add a driver for the Local Bus Controller.marcel2008-10-252-0/+368
| | | | Obtained from: Juniper Networks, Inc.
* Assign 0xff800000-0xffffffff to the LBC controller. That's wheremarcel2008-10-251-0/+4
| | | | the NOR flash lives by default.
* In mmu_booke_mapdev(), handle mappings that cannot be representedmarcel2008-10-251-5/+16
| | | | | by a single TLB entry. The boot ROM on the MPC85555CDS is 8MB, for example, and in order to map that we need 2 4MB TLB entries.
* Prevent the OF syscons module from trying to attach to real devices on thenwhitehorn2008-10-151-0/+5
| | | | nexus by only attaching to a device with no OF node.
* Convert PowerPC AIM PCI and nexus busses to standard OFW bus interface. Thisnwhitehorn2008-10-1417-442/+514
| | | | | | | | | | | simplifies certain device attachments (Kauai ATA, for instance), and makes possible others on new hardware. On G5 systems, there are several otherwise standard PCI devices (Serverworks SATA) that will not allow their interrupt properties to be written, so this information must be supplied directly from Open Firmware. Obtained from: sparc64
* Remove ipi_all() and ipi_self() as the former hasn't been used atmarius2008-09-283-38/+0
| | | | | | | | | | | all to date and the latter also is only used in ia64 and powerpc code which no longer serves a real purpose after bring-up and just can be removed as well. Note that architectures like sun4u also provide no means of implementing IPI'ing a CPU itself natively in the first place. Suggested by: jhb Reviewed by: arch, grehan, jhb
* Unbreak support for G4s without an L3 cache. L3 cache support was introducednwhitehorn2008-09-281-6/+5
| | | | | | with, and limited to, the Motorola/Freescale 745x family. Reported by: Marco Trillo
* Expand the DBDMA API to allow setting device-dependent control bits. Whilenwhitehorn2008-09-272-6/+56
| | | | | | | here, clean up and document this a little. Submitted by: Marco Trillo MFC after: 1 week
* Add DMA support for Apple built-in ATA controllers.nwhitehorn2008-09-274-34/+795
| | | | | Tested by: grehan, marcotrillo@gmail.com MFC after: 1 month
* Replace all calls to minor() with dev2unit().ed2008-09-271-3/+3
| | | | | | | | | | | | | | | After I removed all the unit2minor()/minor2unit() calls from the kernel yesterday, I realised calling minor() everywhere is quite confusing. Character devices now only have the ability to store a unit number, not a minor number. Remove the confusion by using dev2unit() everywhere. This commit could also be considered as a bug fix. A lot of drivers call minor(), while they should actually be calling dev2unit(). In -CURRENT this isn't a problem, but it turns out we never had any problem reports related to that issue in the past. I suspect not many people connect more than 256 pieces of the same hardware. Reviewed by: kib
* Change the static struct sysentvec and struct Elf_Brandinfo initializerskib2008-09-241-46/+47
| | | | | | | | | | | to the C99 style. At least, it is easier to read sysent definitions that way, and search for the actual instances of sigcode etc. Explicitely initialize sysentvec.sv_maxssiz that was missed in most sysvecs. No objection from: jhb MFC after: 1 month
* Allow the cacheline size on PowerPC to be set at runtime. This is essential fornwhitehorn2008-09-244-46/+20
| | | | | supporting 64-bit CPUs, which often have 128-byte cache lines instead of the standard 32.
* Improve rev 183168, so that if /chosen/stdout is connected to the serialsobomax2008-09-231-6/+5
| | | | | | | | port by OF the syscons won't take over console. Only attach syscons to "screen" if /chosen/stdout is not connected, which could be the case when loader(8) is booted directly from the OF. This fixes Marcel's Xserver. Reported by: marcel
* In preparation for PowerPC G5 support, allow PVO objects to contain pagenwhitehorn2008-09-233-54/+62
| | | | table entries for both the 32-bit and 64-bit AIM MMUs.
* Change the DBDMA API to allow DBDMA registers in a subregion of a resource. ↵nwhitehorn2008-09-233-9/+12
| | | | | | This is necessary to allow future support of DMA for the various Apple on-board ATA controllers. MFC after: 1 week
* Unbreak G3 support. G3 processors don't have an L3 cache, so we shouldn't ↵nwhitehorn2008-09-221-3/+8
| | | | | | try to program it. Approved by: marcel (mentor)
* When attaching framebuffer to "/chosen/stdout" node fails, try attachingsobomax2008-09-191-2/+10
| | | | | | | to "screen" node directly. The problem is that by default OF on some (all?) Macs either doesn't provide "/chosen/stdout" or redirects it somewhere, unless you boot in manual mode via CMD-ALT-O-F. It's nice to see normal FreeBSD boot output instead of blank gray screen.
* o When not making a translation cache-inhibit and guarded (PTE_I|PTE_G)marcel2008-09-161-40/+42
| | | | | | | | | | | | | make it memory-coherency enforced (PTE_M). This is required for SMP to work. o Serialize tlbie operations and implement the tlbie operation in a function called tlbie(). Hardware can end up in a live-lock if between the tlbsync and subsequent sync on one processor another processor executes a tlbie or tlbsync. o Eliminate the following defines: TLBIE, TLBSYNC, SYNC and EIEIO Use either inline assembly statements or inline functions defined in <machine/cpufunc.h>
* Rewrite cpudep_ap_bootstrap(). We now enable L3, L2, L1D and L1Imarcel2008-09-161-14/+110
| | | | | | | | | | | | | caches if not yet enabed. This is required for coherency and atomic operations to work, not to mention performance. We use the L2 and L3 cache settings of the BSP to configure the APs caches. Can't be bad. Program NAP and not DOZE. DOZE is present only on earlier CPUs and the bit is reserved on the MPC7441 & MPC7451. NAP will do bus snooping to keep caches coherent. Program the PIR with the cpuid. This may not be necessary...
* o In decr_get_timecount() only read the low timebase register.marcel2008-09-161-4/+9
| | | | | | | We're only returning a 32-bit counter. o In decr_intr(), manually perform LICM, so that we don't test a loop invariant condition inside a loop. o Include <machine/smp.h>
* Set pcpup->pc_curthread and pcpup->pc_curpcb before callingmarcel2008-09-161-3/+3
| | | | | pmap_activate. While pmap_activate doesn't need either, we do need a valid curthread if we enable KTR_PMAP.
* o Synchronize the APs timebase and decrementer values with the BSP.marcel2008-09-161-2/+13
| | | | | o Don't set/get the PIR register. It's CPU dependent. o Also initialize pcpup->pc_curpcb, in case it's dereferenced.
* In powerpc_get_pcpup(), make the inline assembly statementmarcel2008-09-161-1/+1
| | | | | | | | | | | | | | volatile so that the compiler won't perform CSE. For SMP, this may result in us accessing the wrong PCPU and as such results in a bogus curthread value. Note that getting curthread is not quite MP-safe in the sense that it requires two instructions that aren't performed atomically. The first instruction gets the address of the PCPU structure and the second instruction dereferences that pointer to get curthread. If a thread is switched-out in between these instructions and switched-in on a different CPU, we still get the wrong curthread.
* Remove the tracing from the AP startup. The AP is knownmarcel2008-09-165-91/+12
| | | | | | to start and the tracing can interfere with AP startup. Instead, use the available space in the reset vector for the initial stack.
* o Remove SPR_TSR & SPR_TCR for AIM.marcel2008-09-151-8/+23
| | | | | o Remove SPR_HID2. o Add more SPR_L3CR bit definitions.
* Dont worry about PSL_RI (restartable interrupt indicator) inmarcel2008-09-153-6/+3
| | | | | | | | common PowerPC code when all we want to achieve is to enable external interrupts. We can set PSL_RI at any time before we allow interrupts and/or exceptions, so move it to the AIM specific initialization and do it when we also set PSL_ME (machine check enable).
* Rename cpu_config_l2cr() to cpu_print_cacheinfo(). We're notmarcel2008-09-151-103/+47
| | | | | | | | configuring the L2 cache on the BSP. Nor the L3 cache. We merely print the settings. Save the L2 and L3 cache configuration in global values so that we know how to configure the cache on APs.
* Remove debugging code.marcel2008-09-141-15/+7
|
* Trace interrupts with KTR_INTR.marcel2008-08-311-0/+2
|
* Remove redundant KTR statements.marcel2008-08-311-6/+0
|
* Trace all PMAP calls using KTR_PMAP.marcel2008-08-311-2/+92
|
* Remove restore_intr(). We have intr_restore()...marcel2008-08-311-7/+0
|
* In db_show_mdpcpu(), print MD fields.marcel2008-08-301-0/+4
|
* Whitespace fixes.marcel2008-08-301-12/+12
|
* Call powerpc_sync() instead of using an asm statement.marcel2008-08-301-1/+1
|
* Add powerpc_sync() as an inline function.marcel2008-08-301-0/+7
|
* Don't clear PSL_RI. Disabling external interruptsmarcel2008-08-301-1/+1
| | | | doesn't make exceptions unrecoverable.
* Move initialization of tlb0, ptbl_bufs and kernel_pdir regions after we areraj2008-08-281-6/+14
| | | | | | | 100% sure that TLB1 mapping covers for them; previously we could lock the CPU with an untranslated references. Obtained from: Semihalf
* Improve kernel stack handling on e500.raj2008-08-263-24/+56
| | | | | | | | | | - Allocate thread0.td_kstack in pmap_bootstrap(), provide guard page - Switch to thread0.td_kstack as soon as possible i.e. right after return from e500_init() and before mi_startup() happens - Clean up temp stack area - Other minor cosmetics in machdep.c Obtained from: Semihalf
OpenPOWER on IntegriCloud