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* Fix pmap_page_set_memattr() behavior in the presence of fictitious pagesnwhitehorn2010-10-012-42/+20
| | | | | | by just caching the mode for later use by pmap_enter(), following amd64. While here, correct some mismerges from mmu_oea64 -> mmu_oea and clean up some dead code found while fixing the fictitious page behavior.
* Add support for memory attributes (pmap_mapdev_attr() and friends) onnwhitehorn2010-09-307-51/+290
| | | | | PowerPC/AIM. This is currently stubbed out on Book-E, since I have no idea how to implement it there.
* Fix bogus error message from bus_dmamem_alloc() about incorrect alignment.neel2010-09-291-1/+1
| | | | | | | | | The check for alignment should be made against the physical address and not the virtual address that maps it. Sponsored by: NetApp Submitted by: Will McGovern (will at netapp dot com) Reviewed by: mjacob, jhb
* Follow r213098, kernel POSIX semaphore module is no longerdavidxu2010-09-261-1/+0
| | | | needed.
* Now userland POSIX semaphore is based on umtx. The kernel moduledavidxu2010-09-241-1/+0
| | | | | is only used to support binary compatible, if want to run old binary, you need to kldload the module.
* Split the SLB mirror cache into two kinds of object, one for kernel mapsnwhitehorn2010-09-167-79/+110
| | | | | | | which are similar to the previous ones, and one for user maps, which are arrays of pointers into the SLB tree. This changes makes user SLB updates atomic, closing a window for memory corruption. While here, rearrange the allocation functions to make context switches faster.
* Replace the SLB backing store splay tree used on 64-bit PowerPC AIMnwhitehorn2010-09-166-166/+370
| | | | | | | | hardware with a lockless sparse tree design. This marginally improves the performance of PMAP and allows copyin()/copyout() to run without acquiring locks when used on wired mappings. Submitted by: mdf
* Increase register access delay to deal with the high-latency I2Candreast2010-09-151-1/+1
| | | | | | chipset found in some models of Powermac G5. Approved by: nwhitehorn (mentor)
* Introduce inheritance into the PowerPC MMU kobj interface.grehan2010-09-154-26/+34
| | | | | | | | | | | | | | | | | include/mmuvar.h - Change the MMU_DEF macro to also create the class definition as well as define the DATA_SET. Add a macro, MMU_DEF_INHERIT, which has an extra parameter specifying the MMU class to inherit methods from. Update the comments at the start of the header file to describe the new macros. booke/pmap.c aim/mmu_oea.c aim/mmu_oea64.c - Collapse mmu_def_t declaration into updated MMU_DEF macro The MMU_DEF_INHERIT macro will be used in the PS3 MMU implementation to allow it to inherit the stock powerpc64 MMU methods. Reviewed by: nwhitehorn
* Resurrect PSIM support by moving the cacheline size-detection warninggrehan2010-09-141-2/+10
| | | | | printf outside of the MMU-disabled region. A call into OpenFirmware with the MMU off resulted in an internal PSIM assert.
* Fix a missing set of parantheses that could cause recent versions of libthrnwhitehorn2010-09-131-2/+2
| | | | | to crash deferencing a NULL pointer to the user context on powerpc64 systems with COMPAT_FREEBSD32 defined.
* Fix a subtle bug uncovered by the recent one-shot timer import in whichnwhitehorn2010-09-131-3/+0
| | | | | | | | | any spin locks acquired between the enabling of interrupts in machdep_ap_bootstrap() and the invocation of the scheduler would fail to have interrupts disabled due to the fake spinlock already held by the idle thread. sched_throw(NULL) will enable interrupts by itself when exiting this spinlock, so just let it do that and don't enable interrupts here.
* Change call order to enable interrupts only after timer being programmed.mav2010-09-131-3/+3
| | | | Submitted by: nwhitehorn
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-134-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main goal of this is to generate timer interrupts only when there is some work to do. When CPU is busy interrupts are generating at full rate of hz + stathz to fullfill scheduler and timekeeping requirements. But when CPU is idle, only minimum set of interrupts (down to 8 interrupts per second per CPU now), needed to handle scheduled callouts is executed. This allows significantly increase idle CPU sleep time, increasing effect of static power-saving technologies. Also it should reduce host CPU load on virtualized systems, when guest system is idle. There is set of tunables, also available as writable sysctls, allowing to control wanted event timer subsystem behavior: kern.eventtimer.timer - allows to choose event timer hardware to use. On x86 there is up to 4 different kinds of timers. Depending on whether chosen timer is per-CPU, behavior of other options slightly differs. kern.eventtimer.periodic - allows to choose periodic and one-shot operation mode. In periodic mode, current timer hardware taken as the only source of time for time events. This mode is quite alike to previous kernel behavior. One-shot mode instead uses currently selected time counter hardware to schedule all needed events one by one and program timer to generate interrupt exactly in specified time. Default value depends of chosen timer capabilities, but one-shot mode is preferred, until other is forced by user or hardware. kern.eventtimer.singlemul - in periodic mode specifies how much times higher timer frequency should be, to not strictly alias hardclock() and statclock() events. Default values are 2 and 4, but could be reduced to 1 if extra interrupts are unwanted. kern.eventtimer.idletick - makes each CPU to receive every timer interrupt independently of whether they busy or not. By default this options is disabled. If chosen timer is per-CPU and runs in periodic mode, this option has no effect - all interrupts are generating. As soon as this patch modifies cpu_idle() on some platforms, I have also refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions (if supported) under high sleep/wakeup rate, as fast alternative to other methods. It allows SMP scheduler to wake up sleeping CPUs much faster without using IPI, significantly increasing performance on some highly task-switching loads. Tested by: many (on i386, amd64, sparc64 and powerc) H/W donated by: Gheorghe Ardelean Sponsored by: iXsystems, Inc.
* ATAPI DMA does not seem to work completely reliably on Shasta controllers,nwhitehorn2010-09-111-1/+3
| | | | especially in conjunction with ATA_CAM, so disable it for now.
* Change OF_interpret() to also take an array of cell_t (missed in r209801).marius2010-09-111-4/+3
| | | | Reviewed by: nwhitehorn
* Fix the build after r212453. IPI_STATCLOCK declaration is still neededmav2010-09-111-0/+1
| | | | | | for build, though not really used. Submitted by: andreast
* Update PowerPC event timer code to use new event timers infrastructure.mav2010-09-1111-118/+285
| | | | | | Reviewed by: nwitehorn Tested by: andreast H/W donated by: Gheorghe Ardelean
* bus_add_child: change type of order parameter to u_intavg2010-09-101-2/+2
| | | | | | | | | | This reflects actual type used to store and compare child device orders. Change is mostly done via a Coccinelle (soon to be devel/coccinelle) semantic patch. Verified by LINT+modules kernel builds. Followup to: r212213 MFC after: 10 days
* Reorder statistics tracking and table lock acquisitions already in placenwhitehorn2010-09-091-4/+6
| | | | to avoid race conditions updating the PVO statistics.
* Fix a printf specifier on 64-bit systems.nwhitehorn2010-09-081-1/+1
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* Fix a typo in the original import of this code from NetBSD that caused thenwhitehorn2010-09-082-2/+4
| | | | | | | | | wrong element of the VSID bitmap array to be examined after a collision, leading to reallocation of in-use VSIDs under some circumstances, with attendant memory corruption. Also add an assert to check for this kind of problem in the future. MFC after: 4 days
* Fix an error made in r209975 related to context ID allocation for 64-bitnwhitehorn2010-09-071-4/+7
| | | | | | | | PowerPC CPUs running a 32-bit kernel. This bug could cause in-use VSIDs to be allocated again to another process, causing memory space overlaps and corruption. Reported by: linimon
* Fix the same race condition on 32-bit AIM CPUs that was fixed for 64-bitnwhitehorn2010-09-061-0/+7
| | | | ones in r211967 involving VSID allocation.
* Make nexus report name and compat fields as pnpinfo for devices on themav2010-09-051-0/+2
| | | | first level of hierarchy, same as done on deeper levels.
* - Bump MAXCPU to 4. Tested on a quad G5 with both 32 and 64-bit kernels.grehan2010-09-033-4/+12
| | | | | | | | A make buildkernel -j4 uses ~360% CPU. - Bracket the AP spinup printf with a mutex to avoid garbled output. - Enable SMP by default on powerpc64. Reviewed by: nwhitehorn
* Restructure how reset and poweroff are handled on PowerPC systems, sincenwhitehorn2010-08-3112-89/+170
| | | | | | | | | | | | | | | | | the existing code was very platform specific, and broken for SMP systems trying to reboot from KDB. - Add a new PLATFORM_RESET() method to the platform KOBJ interface, and migrate existing reset functions into platform modules. - Modify the OF_reboot() routine to submit the request by hand to avoid the IPIs involved in the regular openfirmware() routine. This fixes reboot from KDB on SMP machines. - Move non-KDB reset and poweroff functions on the Powermac platform into the relevant power control drivers (cuda, pmu, smu), instead of using them through the Open Firmware backdoor. - Rename platform_chrp to platform_powermac since it has become increasingly Powermac specific. When we gain support for IBM systems, we will grow a new platform_chrp.
* Remove some code made obsolete by the powerpc64 import.nwhitehorn2010-08-311-677/+0
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* Missed one place the SLB lock should be held in r211967.nwhitehorn2010-08-311-6/+8
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* Avoid a race in the allocation of new segment IDs that could result innwhitehorn2010-08-291-0/+5
| | | | | | memory corruption on heavily loaded SMP systems. MFC after: 2 weeks
* pmap_mapdev() does not appear to actually need GIANT to be held here,nwhitehorn2010-08-271-2/+0
| | | | | | and asserting that is held breaks drm. MFC after: 2 weeks
* Remove unused KTRACE includes.jhb2010-08-192-9/+0
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* Unbreak the LINT kernel on powerpc64. Note that the LINT kernelnwhitehorn2010-08-192-1/+6
| | | | | | | configuration is TARGET_ARCH specific and must be generated with TARGET_ARCH set. Reviewed by: imp
* Supply some useful information to the started image using ELF aux vectors.kib2010-08-171-2/+8
| | | | | | | | In particular, provide pagesize and pagesizes array, the canary value for SSP use, number of host CPUs and osreldate. Tested by: marius (sparc64) MFC after: 1 month
* Update various places that store or manipulate CPU masks to use cpumask_tjhb2010-08-111-2/+2
| | | | | instead of int or u_int. Since cpumask_t is currently u_int on all platforms this should just be a cosmetic change.
* Add a new ipi_cpu() function to the MI IPI API that can be used to send anjhb2010-08-062-0/+9
| | | | | | | | | | | | IPI to a specific CPU by its cpuid. Replace calls to ipi_selected() that constructed a mask for a single CPU with calls to ipi_cpu() instead. This will matter more in the future when we transition from cpumask_t to cpuset_t for CPU masks in which case building a CPU mask is more expensive. Submitted by: peter, sbruno Reviewed by: rookie Obtained from: Yahoo! (x86) MFC after: 1 month
* Improve hash coverage for kernel page table entries by modifying the kernelnwhitehorn2010-07-313-16/+10
| | | | | ESID -> VSID map function. This makes ZFS run stably on PowerPC under heavy loads (repeated simultaneous SVN checkouts and updates).
* Add support for the IBM Full-System Simulator (Mambo). This code has beennwhitehorn2010-07-319-0/+825
| | | | developed against the 970 and Cell simulators.
* Add MALLOC_DEBUG_MAXZONES=8 to powerpc64 GENERIC configuration file.mdf2010-07-301-0/+1
| | | | | Requested by: nwhitehorn Approved by: zml (mentor)
* Add MALLOC_DEBUG_MAXZONES debug malloc(9) option to use multiple umamdf2010-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | zones for each malloc bucket size. The purpose is to isolate different malloc types into hash classes, so that any buffer overruns or use-after-free will usually only affect memory from malloc types in that hash class. This is purely a debugging tool; by varying the hash function and tracking which hash class was corrupted, the intersection of the hash classes from each instance will point to a single malloc type that is being misused. At this point inspection or memguard(9) can be used to catch the offending code. Add MALLOC_DEBUG_MAXZONES=8 to -current GENERIC configuration files. The suggestion to have this on by default came from Kostik Belousov on -arch. This code is based on work by Ron Steinke at Isilon Systems. Reviewed by: -arch (mostly silence) Reviewed by: zml Approved by: zml (mentor)
* Very rough first cut at NUMA support for the physical page allocator. Forjhb2010-07-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | now it uses a very dumb first-touch allocation policy. This will change in the future. - Each architecture indicates the maximum number of supported memory domains via a new VM_NDOMAIN parameter in <machine/vmparam.h>. - Each cpu now has a PCPU_GET(domain) member to indicate the memory domain a CPU belongs to. Domain values are dense and numbered from 0. - When a platform supports multiple domains, the default freelist (VM_FREELIST_DEFAULT) is split up into N freelists, one for each domain. The MD code is required to populate an array of mem_affinity structures. Each entry in the array defines a range of memory (start and end) and a domain for the range. Multiple entries may be present for a single domain. The list is terminated by an entry where all fields are zero. This array of structures is used to split up phys_avail[] regions that fall in VM_FREELIST_DEFAULT into per-domain freelists. - Each memory domain has a separate lookup-array of freelists that is used when fulfulling a physical memory allocation. Right now the per-domain freelists are listed in a round-robin order for each domain. In the future a table such as the ACPI SLIT table may be used to order the per-domain lookup lists based on the penalty for each memory domain relative to a specific domain. The lookup lists may be examined via a new vm.phys.lookup_lists sysctl. - The first-touch policy is implemented by using PCPU_GET(domain) to pick a lookup list when allocating memory. Reviewed by: alc
* When compat32 binary asks for the value of hw.machine_arch, report thekib2010-07-221-0/+5
| | | | | | | | | | | name of 32bit sibling architecture instead of the host one. Do the same for hw.machine on amd64. Add a safety belt debug.adaptive_machine_arch sysctl, to turn the substitution off. Reviewed by: jhb, nwhitehorn MFC after: 2 weeks
* Eliminate FDT_IMMR_VA define.raj2010-07-192-9/+1
| | | | | This removes platform dependencies from <machine>/fdt.h for the benfit of portability.
* Remove obsolete code that sets SHMMAXPGS to a tiny value by defaultnwhitehorn2010-07-131-7/+0
| | | | on PowerPC.
* Add GENERIC kernel config for powerpc64.nwhitehorn2010-07-131-0/+182
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* MFppc64:nwhitehorn2010-07-1371-1019/+5497
| | | | | | | Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
* Fix printf specifier to allow 32/64 bit builds.grehan2010-07-121-1/+1
| | | | Obtained from: projects/ppc64
* Unify ABI-related bits of the Book-E and AIM machdep routinesnwhitehorn2010-07-126-1026/+685
| | | | | | | | (exec_setregs, etc.) in order to simplify the addition of 64-bit support, and possible future extension of the Book-E code to handle hard floating point and Altivec. MFC after: 1 month
* MFppc64:nwhitehorn2010-07-121-3/+31
| | | | | Provide ELF definitions for 64-bit PowerPC. This unbreaks the powerpc loader build.
* Convert Freescale PowerPC platforms to FDT convention.raj2010-07-1124-2220/+1834
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are affected: - MPC8555CDS - MPC8572DS This overhaul covers the following major changes: - All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI. - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data. Note that world for these platforms has to be built WITH_FDT. Reviewed by: imp Sponsored by: The FreeBSD Foundation
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