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* The number after 2 is 3, not 4.nwhitehorn2010-07-091-1/+1
| | | | MFC after: 3 days
* Remove an unnecessary include of opt_psim.h, which is not present onnwhitehorn2010-07-091-1/+0
| | | | powerpc64.
* MFppc64:nwhitehorn2010-07-091-3/+3
| | | | | Minor 64-bit-cleanliness upgrades and support for platform detection on subtly-broken OF implementations like in the Mambo simulator.
* MFppc64:nwhitehorn2010-07-091-7/+7
| | | | | Use longs instead of ints as the native word type in bcopy(). This will expand nicely on 64-bit systems.
* MFppc64:nwhitehorn2010-07-091-3/+3
| | | | | Check if devices are direct-mapped individually instead of just checking the value of hw_direct_map.
* Replace the existing PowerPC busdma implementation with the one fromnwhitehorn2010-07-083-211/+834
| | | | | amd64 (with slight modifications). This provides support for bounce buffers, which are required on systems with RAM above 4 GB.
* Make ofw_syscons work on 64-bit systems.nwhitehorn2010-07-081-3/+3
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* Fix several bugs in the real-mode Open Firmware implementation and providenwhitehorn2010-07-081-157/+325
| | | | | | a virtual-mode version for use on 64-bit systems, which have 32-bit firmware implementations and require similar constraints on addressing to the real-mode implementation.
* Change the argument type to OF_call_method to take an array of cell_tnwhitehorn2010-07-081-4/+3
| | | | | instead of unsigned longs to prepare for platforms where they are not the same.
* It does not actually make sense to provide an IPI facility on non-rootnwhitehorn2010-07-061-4/+3
| | | | PICs, so replace cpuid logic with an assert.
* Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.nwhitehorn2010-07-061-7/+14
| | | | | | | | | Because slave PICs send all interrupts to their CPU 0 output line (which is routed to a pin on the master PIC), changes to per-CPU register banks like EOI on the slave PIC must be accessed for CPU 0, instead of the CPU actually processing the interrupt. Submitted by: Andreas Tobler
* Move the EOI logic when starting ithreads into intr_machdep instead ofnwhitehorn2010-07-064-18/+25
| | | | | relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
* Add a missing conditional. We should not bind the PIC interrupt unlessnwhitehorn2010-07-031-1/+2
| | | | | | the interrupt's PIC (a) exists and (b) is the root PIC. Reported by: Andreas Tobler
* Remove the unneeded header <machine/intr.h>.marcel2010-07-0211-90/+0
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* MFia64:marcel2010-07-011-1/+1
| | | | | When compiling with profiling, we define PROF for userspace and GPROF for the kernel.
* Move prototypes for kern_sigtimedwait() and kern_sigprocmask() tojhb2010-06-302-0/+2
| | | | <sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
* Fix profiling (part 1):marcel2010-06-292-2/+2
| | | | | | o Functions are 4-byte aligned for Book-E. o We get compiled with -DPROF and not -DGPROF if profiling is enabled.
* Assign PCI intline values for ISA interrupts using the new INTR_VEC()marcel2010-06-241-3/+3
| | | | macro.
* Remove debugging printf() -- that is, I assume it was for debugging :-)marcel2010-06-241-2/+0
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* Pass the device_t of the AT PIC driver to atpic_intr() so thatmarcel2010-06-241-5/+2
| | | | | we don't have to use a global variable. Pass a NULL frame pointer to the dispatch function just like openpic(4).
* With openpic(4) using active-low as the default polarity, reconfiguremarcel2010-06-231-2/+9
| | | | | | | | | | the internal interrupt sources as active-high. The internal interrupt sources are disabled when programmed as active-low. Note that the internal interrupts have no sense bit like the external interrupts. We program them as edge-triggered to make sure we write a 0 value to a reserved register. It does not in any way say anything about the sense of internal interrupt.
* Configure interrupts on SMP systems to be distributed among all onlinenwhitehorn2010-06-239-3/+110
| | | | | | CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
* In the attach method, refactor to take into account thatmarcel2010-06-231-3/+10
| | | | | BUS_GET_RESOURCE_LIST() can return a NULL pointer -- and will for MPC85xx kernels.
* Temporarily disable instruction relocation while setting up the kernel'snwhitehorn2010-06-201-1/+6
| | | | | | | | IBAT entry in early boot in order to prevent possible faults from races between the instruction cache and the MMU. PR: powerpc/148003 MFC after: 3 days
* Missed commit in r209310: the IRQ number in INTR_VEC() should havenwhitehorn2010-06-181-1/+1
| | | | | | parantheses around it to allow arithmetic expressions to be passed. Submitted by: Andreas Tobler
* Add MSI support for PCI devices attached to the CPC925 and CPC945 bridgesnwhitehorn2010-06-182-3/+165
| | | | found in Apple and IBM G5 systems.
* Add support for the Keywest I2C controller in Apple uninorth northbridges.nwhitehorn2010-06-181-2/+7
| | | | | | Although the Keywest registers have only 1 byte of content, they are secretly 4-byte registers, which became apparent from them moving on the big-endian Uninorth version of the controller.
* Change the default interrupt polarity on PowerPC systems from high to low.nwhitehorn2010-06-183-12/+24
| | | | | | On Apple systems at least, all the level interrupts are wired active low. Before this change, our PIC programming only worked because Apple hardware ignores the interrupt polarity bit on all interrupts except IRQ 0.
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-1826-107/+288
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Modify the console mouse pointer drawing routine to use single-byte writesnwhitehorn2010-06-151-17/+4
| | | | | | | | | instead of 4-byte ones. Because the mouse pointer can start part way through a character cell, 4-byte memory operations are not necessarily aligned, triggering a fatal alignment exception when the console pointer was moved on PowerPC G5 systems. MFC after: 3 days
* Make SMP work on MPC7400-based Apple desktops like the PowerMac3,3.nwhitehorn2010-06-122-10/+42
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* Relax one of the new assertions in pmap_enter() a little. Specifically,alc2010-06-113-3/+6
| | | | | | allow pmap_enter() to be performed on an unmanaged page that doesn't have VPO_BUSY set. Having VPO_BUSY set really only matters for managed pages. (See, for example, pmap_remove_write().)
* Reduce the scope of the page queues lock and the number ofalc2010-06-103-80/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PG_REFERENCED changes in vm_pageout_object_deactivate_pages(). Simplify this function's inner loop using TAILQ_FOREACH(), and shorten some of its overly long lines. Update a stale comment. Assert that PG_REFERENCED may be cleared only if the object containing the page is locked. Add a comment documenting this. Assert that a caller to vm_page_requeue() holds the page queues lock, and assert that the page is on a page queue. Push down the page queues lock into pmap_ts_referenced() and pmap_page_exists_quick(). (As of now, there are no longer any pmap functions that expect to be called with the page queues lock held.) Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever be passed an unmanaged page. Assert this rather than returning "0" and "FALSE" respectively. ARM: Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH(). Push down the page queues lock inside of pmap_clearbit(), simplifying pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write(). Additionally, this allows for avoiding the acquisition of the page queues lock in some cases. PowerPC/AIM: moea*_page_exits_quick() and moea*_page_wired_mappings() will never be called before pmap initialization is complete. Therefore, the check for moea_initialized can be eliminated. Push down the page queues lock inside of moea*_clear_bit(), simplifying moea*_clear_modify() and moea*_clear_reference(). The last parameter to moea*_clear_bit() is never used. Eliminate it. PowerPC/BookE: Simplify mmu_booke_page_exists_quick()'s control flow. Reviewed by: kib@
* Add Open Firmware PNP info strings to GPIOs and Uninorth cells.nwhitehorn2010-06-062-0/+4
| | | | Submitted by: Andreas Tobler
* Correct a harmless typo introduced when copying code from mmu_oea64.nwhitehorn2010-06-051-1/+1
| | | | | Submitted by: alc MFC after: 8.1-RELEASE
* Don't set PG_WRITEABLE in pmap_enter() unless the page is managed.alc2010-06-051-2/+4
| | | | Correct a typo in a nearby comment on sparc64.
* Add a driver for the CPU temperature sensors attached over I2C on thenwhitehorn2010-06-051-0/+262
| | | | PowerMac 11,2.
* Add support for the I2C busses hanging off Apple system management chips.nwhitehorn2010-06-051-12/+241
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* Utilize the Keywest I2C combined mode for messages with repeated starts.nwhitehorn2010-06-051-8/+57
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* Make sure that interrupt sense settings set after interrupts are enablednwhitehorn2010-06-051-1/+7
| | | | | | | | are respected. This fixes loading the Apple onboard audio driver (snd_ai2s) as a module after boot, which would previously cause a panic. PR: powerpc/146888 MFC after: 5 days
* Don't set PG_WRITEABLE in pmap_enter() unless the page is managed.alc2010-06-052-2/+4
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* In the case that mmu_booke_enter_locked() is changing the attributes of aalc2010-06-011-1/+1
| | | | | | | | | mapping but not changing the physical page being mapped, the wrong flags were being inspected in order to determine whether or not to flush the instruction cache. The effect of looking at the wrong flags was that the instruction cache was never being flushed. Reviewed by: marcel
* Prepare and extend OFW layer for FDT support.raj2010-05-281-2/+3
| | | | | | | | | | | | | o Let OFW_INIT() and OF_init() return status value. o Provide helper routines for 'compatible' property handling. o Only compile OF and OFW code, which is relevant in FDT scenario. o Other minor cosmetics Reviewed by: imp Sponsored by: The FreeBSD Foundation
* Push down page queues lock acquisition in pmap_enter_object() andalc2010-05-263-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pmap_is_referenced(). Eliminate the corresponding page queues lock acquisitions from vm_map_pmap_enter() and mincore(), respectively. In mincore(), this allows some additional cases to complete without ever acquiring the page queues lock. Assert that the page is managed in pmap_is_referenced(). On powerpc/aim, push down the page queues lock acquisition from moea*_is_modified() and moea*_is_referenced() into moea*_query_bit(). Again, this will allow some additional cases to complete without ever acquiring the page queues lock. Reorder a few statements in vm_page_dontneed() so that a race can't lead to an old reference persisting. This scenario is described in detail by a comment. Correct a spelling error in vm_page_dontneed(). Assert that the object is locked in vm_page_clear_dirty(), and restrict the page queues lock assertion to just those cases in which the page is currently writeable. Add object locking to vnode_pager_generic_putpages(). This was the one and only place where vm_page_clear_dirty() was being called without the object being locked. Eliminate an unnecessary vm_page_lock() around vnode_pager_setsize()'s call to vm_page_clear_dirty(). Change vnode_pager_generic_putpages() to the modern-style of function definition. Also, change the name of one of the parameters to follow virtual memory system naming conventions. Reviewed by: kib
* Initial loader(8) support for Flattened Device Tree.raj2010-05-251-0/+1
| | | | | | | | | | o This is disabled by default for now, and can be enabled using WITH_FDT at build time. o Tested with ARM and PowerPC. Reviewed by: imp Sponsored by: The FreeBSD Foundation
* Roughly half of a typical pmap_mincore() implementation is machine-alc2010-05-245-50/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | independent code. Move this code into mincore(), and eliminate the page queues lock from pmap_mincore(). Push down the page queues lock into pmap_clear_modify(), pmap_clear_reference(), and pmap_is_modified(). Assert that these functions are never passed an unmanaged page. Eliminate an inaccurate comment from powerpc/powerpc/mmu_if.m: Contrary to what the comment says, pmap_mincore() is not simply an optimization. Without a complete pmap_mincore() implementation, mincore() cannot return either MINCORE_MODIFIED or MINCORE_REFERENCED because only the pmap can provide this information. Eliminate the page queues lock from vfs_setdirty_locked_object(), vm_pageout_clean(), vm_object_page_collect_flush(), and vm_object_page_clean(). Generally speaking, these are all accesses to the page's dirty field, which are synchronized by the containing vm object's lock. Reduce the scope of the page queues lock in vm_object_madvise() and vm_page_dontneed(). Reviewed by: kib (an earlier version)
* Reorganize syscall entry and leave handling.kib2010-05-234-174/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend struct sysvec with three new elements: sv_fetch_syscall_args - the method to fetch syscall arguments from usermode into struct syscall_args. The structure is machine-depended (this might be reconsidered after all architectures are converted). sv_set_syscall_retval - the method to set a return value for usermode from the syscall. It is a generalization of cpu_set_syscall_retval(9) to allow ABIs to override the way to set a return value. sv_syscallnames - the table of syscall names. Use sv_set_syscall_retval in kern_sigsuspend() instead of hardcoding the call to cpu_set_syscall_retval(). The new functions syscallenter(9) and syscallret(9) are provided that use sv_*syscall* pointers and contain the common repeated code from the syscall() implementations for the architecture-specific syscall trap handlers. Syscallenter() fetches arguments, calls syscall implementation from ABI sysent table, and set up return frame. The end of syscall bookkeeping is done by syscallret(). Take advantage of single place for MI syscall handling code and implement ptrace_lwpinfo pl_flags PL_FLAG_SCE, PL_FLAG_SCX and PL_FLAG_EXEC. The SCE and SCX flags notify the debugger that the thread is stopped at syscall entry or return point respectively. The EXEC flag augments SCX and notifies debugger that the process address space was changed by one of exec(2)-family syscalls. The i386, amd64, sparc64, sun4v, powerpc and ia64 syscall()s are changed to use syscallenter()/syscallret(). MIPS and arm are not converted and use the mostly unchanged syscall() implementation. Reviewed by: jhb, marcel, marius, nwhitehorn, stas Tested by: marcel (ia64), marius (sparc64), nwhitehorn (powerpc), stas (mips) MFC after: 1 month
* Now that single-threaded access to firmware is enforced bynwhitehorn2010-05-211-14/+0
| | | | IPI_RENDEZVOUS, the ofw mutex is irrelevant.
* Fix a long-standing bug in the PowerPC OFW call function on SMP machinesnwhitehorn2010-05-201-5/+64
| | | | | | | | | | | | | | | where running ofwdump could cause hangs by forcing all secondary CPUs into a busy wait with interrupts off during the call. Following section 8.4 of the Open Firmware PowerPC processor binding, the firmware is free to overwrite the system interrupt handlers during OF calls, restoring the OS handlers on exit. On single CPU systems, this process is invisible to the operating system. On multiple CPU systems, taking any exception on a secondary CPU while an OF call is in progress ends with that exception vectored into OF, resulting in a slow movement of the entire system into firmware context and a machine hang. MFC after: 3 days
* Correct a typo.nwhitehorn2010-05-191-1/+1
| | | | Pointy hat to: me
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