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* Now that all platforms use genclock, shuffle things around slightlyphk2008-04-223-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for better structure. Much of this is related to <sys/clock.h>, which should really have been called <sys/calendar.h>, but unless and until we need the name, the repocopy can wait. In general the kernel does not know about minutes, hours, days, timezones, daylight savings time, leap-years and such. All that is theoretically a matter for userland only. Parts of kernel code does however care: badly designed filesystems store timestamps in local time and RTC chips almost universally track time in a YY-MM-DD HH:MM:SS format, and sometimes in local timezone instead of UTC. For this we have <sys/clock.h> <sys/time.h> on the other hand, deals with time_t, timeval, timespec and so on. These know only seconds and fractions thereof. Move inittodr() and resettodr() prototypes to <sys/time.h>. Retain the names as it is one of the few surviving PDP/VAX references. Move startrtclock() to <machine/clock.h> on relevant platforms, it is a MD call between machdep.c/clock.c. Remove references to it elsewhere. Remove a lot of unnecessary <sys/clock.h> includes. Move the machdep.disable_rtc_set sysctl to subr_rtc.c where it belongs. XXX: should be kern.disable_rtc_set really, it's not MD.
* Make genclock standard on all platforms.phk2008-04-212-2/+0
| | | | Thanks to: grehan & marcel for platform support on ia64 and ppc.
* Switch to using genclock. Have nexus double as clock device formarcel2008-04-213-77/+78
| | | | | | now. While here, add a proper attach() method to nexus. Requested by: phk
* Simplify the pmap_zero_page family of functions by making use ofmarcel2008-04-171-160/+6
| | | | | | | | the fact that we have a 1:1 mapping by virtue of the BATs. Eliminate the now unused moea_rkva_alloc(), moea_pa_map() and moea_pa_unmap() functions. Pointed out by: grehan.
* Allocate a stack (with optional guard pages) for thread0 andmarcel2008-04-163-70/+60
| | | | switch to it before calling mi_startup().
* Get rid of an empty RTC implementation and hook up genclock instead.phk2008-04-132-44/+1
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* - Add the interrupt vector number to intr_event_create so MI code canjeff2008-04-111-1/+1
| | | | | | | | | | | | lookup hard interrupt events by number. Ignore the irq# for soft intrs. - Add support to cpuset for binding hardware interrupts. This has the side effect of binding any ithread associated with the hard interrupt. As per restrictions imposed by MD code we can only bind interrupts to a single cpu presently. Interrupts can be 'unbound' by binding them to all cpus. Reviewed by: jhb Sponsored by: Nokia
* Fix copy-n-paste typos in free text.marcel2008-04-101-3/+3
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* Include <sys/types.h> before <sys/systm.h> to get typedefs requiredgrehan2008-04-098-8/+8
| | | | by new atomic.h. Fixes tinderbox LINT build.
* Reimplement atomic_add, atomic_clear, atomic_set and atomic_subtractmarcel2008-04-091-272/+294
| | | | | | | | so that all implemented variants have proper prototypes. The 8-bit, 16-bit and 64-bit variants are not implemented. This really fixes the current build breakages caused by type casting and struct aliasing rules.
* Quick fix for the kernel build breakage in netgraph and themarcel2008-04-081-2/+4
| | | | | | aliasing warning in libthr. A more elaborate fix is in the works that makes sure that all variants have proper inline functions with proper types.
* Add a MI intr_event_handle() routine for the non-INTR_FILTER case. Thisjhb2008-04-051-45/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | allows all the INTR_FILTER #ifdef's to be removed from the MD interrupt code. - Rename the intr_event 'eoi', 'disable', and 'enable' hooks to 'post_filter', 'pre_ithread', and 'post_ithread' to be less x86-centric. Also, add a comment describe what the MI code expects them to do. - On amd64, i386, and powerpc this is effectively a NOP. - On arm, don't bother masking the interrupt unless the ithread is scheduled in the non-INTR_FILTER case to match what INTR_FILTER did. Also, don't bother unmasking the interrupt in the post_filter case if we never masked it. The INTR_FILTER case had been doing this by having arm_unmask_irq for the post_filter (formerly 'eoi') hook. - On ia64, stray interrupts are now masked for the non-INTR_FILTER case. They were already masked in the INTR_FILTER case. - On sparc64, use the a NULL pre_ithread hook and use intr_enable_eoi() for both the 'post_filter' and 'post_ithread' hooks to match what the non-INTR_FILTER code did. - On sun4v, retire the ithread wrapper hack by using an appropriate 'post_ithread' hook instead (it's what 'post_ithread'/'enable' was designed to do even in 5.x). Glanced at by: piso Reviewed by: marius Requested by: marius [1], [5] Tested on: amd64, i386, arm, sparc64
* Align functions to 16-byte boundaries due to profiling granularity.marcel2008-04-031-1/+1
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* Set sc_psim so that the openpic core can correct the off-by-onemarcel2008-04-031-0/+5
| | | | error in the number of IRQs that PSIM gives us.
* Add kernel module support for nfslockd and krpc. Use the module systemdfr2008-03-271-0/+1
| | | | | | | to detect (or load) kernel NLM support in rpc.lockd. Remove the '-k' option to rpc.lockd and make kernel NLM the default. A user can still force the use of the old user NLM by building a kernel without NFSLOCKD and/or removing the nfslockd.ko module.
* When building a kernel module, define MAXCPU the same as SMP sojb2008-03-271-2/+2
| | | | that modules work with and without SMP.
* The "free-lance" timer in the i8254 is only used for the speakerphk2008-03-263-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | these days, so de-generalize the acquire_timer/release_timer api to just deal with speakers. The new (optional) MD functions are: timer_spkr_acquire() timer_spkr_release() and timer_spkr_setfreq() the last of which configures the timer to generate a tone of a given frequency, in Hz instead of 1/1193182th of seconds. Drop entirely timer2 on pc98, it is not used anywhere at all. Move sysbeep() to kern/tty_cons.c and use the timer_spkr*() if they exist, and do nothing otherwise. Remove prototypes and empty acquire-/release-timer() and sysbeep() functions from the non-beeping archs. This eliminate the need for the speaker driver to know about i8254frequency at all. In theory this makes the speaker driver MI, contingent on the timer_spkr_*() functions existing but the driver does not know this yet and still attaches to the ISA bus. Syscons is more tricky, in one function, sc_tone(), it knows the hz and things are just fine. In the other function, sc_bell() it seems to get the period from the KDMKTONE ioctl in terms if 1/1193182th second, so we hardcode the 1193182 and leave it at that. It's probably not important. Change a few other sysbeep() uses which obviously knew that the argument was in terms of i8254 frequency, and leave alone those that look like people thought sysbeep() took frequency in hertz. This eliminates the knowledge of i8254_freq from all but the actual clock.c code and the prof_machdep.c on amd64 and i386, where I think it would be smart to ask for help from the timecounters anyway [TBD].
* Simplify the interrupt code a bit:jhb2008-03-171-6/+1
| | | | | | | | | | | | - Always include the ie_disable and ie_eoi methods in 'struct intr_event' and collapse down to one intr_event_create() routine. The disable and eoi hooks simply aren't used currently in the !INTR_FILTER case. - Expand 'disab' to 'disable' in a few places. - Use function casts for arm and i386:intr_eoi_src() instead of wrapper routines since to trim one extra indirection. Compiled on: {arm,amd64,i386,ia64,ppc,sparc64} x {FILTER, !FILTER} Tested on: {amd64,i386} x {FILTER, !FILTER}
* Make remote GDB work for AIM processors. For BookE, the kernelmarcel2008-03-172-43/+27
| | | | | | | | will have a special section, named .PPC.EMB.apuinfo, which will tell GDB that a BookE processor is targeted and which will result in GDB using a different register definition. In order to support remote GDB for BookE, we need the GDB stub in the kernel look for that section and use the BookE definitions.
* Implement atomic_fetchadd_long() for all architectures and document it.pjd2008-03-161-0/+2
| | | | Reviewed by: attilio, jhb, jeff, kris (as a part of the uidinfo_waitfree.patch)
* In keeping with style(9)'s recommendations on macros, use a ';'rwatson2008-03-163-3/+3
| | | | | | | | | after each SYSINIT() macro invocation. This makes a number of lightweight C parsers much happier with the FreeBSD kernel source, including cflow's prcc and lxr. MFC after: 1 month Discussed with: imp, rink
* Add preliminary support for binding interrupts to CPUs:jhb2008-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add a new intr_event method ie_assign_cpu() that is invoked when the MI code wishes to bind an interrupt source to an individual CPU. The MD code may reject the binding with an error. If an assign_cpu function is not provided, then the kernel assumes the platform does not support binding interrupts to CPUs and fails all requests to do so. - Bind ithreads to CPUs on their next execution loop once an interrupt event is bound to a CPU. Only shared ithreads are bound. We currently leave private ithreads for drivers using filters + ithreads in the INTR_FILTER case unbound. - A new intr_event_bind() routine is used to bind an interrupt event to a CPU. - Implement binding on amd64 and i386 by way of the existing pic_assign_cpu PIC method. - For x86, provide a 'intr_bind(IRQ, cpu)' wrapper routine that looks up an interrupt source and binds its interrupt event to the specified CPU. MI code can currently (ab)use this by doing: intr_bind(rman_get_start(irq_res), cpu); however, I plan to add a truly MI interface (probably a bus_bind_intr(9)) where the implementation in the x86 nexus(4) driver would end up calling intr_bind() internally. Requested by: kmacy, gallatin, jeff Tested on: {amd64, i386} x {regular, INTR_FILTER}
* Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on whatraj2008-03-124-1/+37
| | | | | | | | | | | | might be currently programmed into the registers. Underlying firmware (U-Boot) would typically program MAC address into the first unit only, and others are left uninitialized. It is now possible to retrieve and program MAC address for all units properly, provided they were passed on in the bootinfo metadata. Reviewed by: imp, marcel Approved by: cognet (mentor)
* Remove kernel support for M:N threading.jeff2008-03-125-15/+2
| | | | | | | | While the KSE project was quite successful in bringing threading to FreeBSD, the M:N approach taken by the kse library was never developed to its full potential. Backwards compatibility will be provided via libmap.conf for dynamically linked binaries and static binaries will be broken.
* In intr_lookup(), when adding an IRQ to powerpc_intrs[], alsomarcel2008-03-111-7/+10
| | | | | | | set a default name. If the IRQ is added as a consequence of configurating the IRQ without there ever being a handler assigned to it, we will not have a name. This breaks the fragile intrcnt/intrnames logic.
* Don't use in32() and out32() when writing to the CCSRBAR. Themarcel2008-03-091-9/+26
| | | | | | in*() and out*() primitives should not be used, other than by ISA drivers. In this case they were used for memory-mapped I/O and were not even used in the spirit of the primitives.
* Enable the D-cache and I-cache when not already enabled.marcel2008-03-081-3/+28
| | | | | | | | | It so happens that U-Boot disables the D-cache when booting an ELF image, so this change makes sure we run with the D-cache enabled from now on. It shows too... While here, remove the duplicate definition of the hw.model sysctl.
* For AIM, have cpu_idle() set MSR_POW when the powerpc_pow_enabledmarcel2008-03-074-11/+16
| | | | | | variable is set. On my Mac Mini this puts the CPU in NAP mode when the kernel is idle and, any technical or environmental reasons aside, avoids that I have to listen to the fan all day :-)
* Add support for the BUS_CONFIG_INTR() method to the platform and tomarcel2008-03-079-42/+136
| | | | | openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
* Add a catch-all for PCPU_MD_FIELDS. While we expect this to bemarcel2008-03-061-0/+7
| | | | | | | | | used in the kernel only (by virtue of checking for _KERNEL), ports like lsof (part of gtop) cheat. It sets _KERNEL, but does not set either AIM or E500. As such, PCPU_MD_FIELDS didn't get defined and the build broke. The catch-all is to define PCPU_MD_FIELDS with a dummy integer when at the end of line we ended up without a definition for it.
* o We don't have to keep track of the PIC, nor do we have to make suremarcel2008-03-051-28/+39
| | | | | | | it's probed first. The PowerPC platform code deals with everything. As such, probe devices in order of their location in the memory map. o Refactor the ocpbus_alloc_resource for readability and make sure we set the RID in the resource as per the new convention.
* o Various fixes related to PCI Express:marcel2008-03-051-37/+65
| | | | | | | | | | | | | | | | | | | | | | | | | - Even for the PCI Express host controller we need to use bus 0 for configuration space accesses to devices directly on the host controller's bus. - Pass the maximum number of slots to pci_ocp_init() because the caller knows how many slots the bus has. Previously a PCI or PCI-X bus underneath a PCI Express host controller would not be enumerated properly. o Pull the interrupt routing logic out of pci_ocp_init() and into its own function. The logic is not quite right and is expected to be a bit more complex. o Fix/add support for PCI domains. The PCI domain is the unit number as per other PCI host controller drivers. As such, we can use logical bus numbers again and don't have to guarantee globally unique bus numbers. Remove pci_ocp_busnr. Return the highest bus number ito the caller of pci_ocp_init() now that we don't have a global variable anymore. o BAR programming fixes: - Non-type0 headers have at most 1 BAR, not 0. - First write ~0 to the BAR in question and then read back its size. Obtained from: Juniper Networks (mostly)
* Also comment-out options MPC85XX. We don't define CCSRBAR_* without E500.marcel2008-03-041-1/+1
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* Comment-out cpu E500. We can't yet build it with AIM at the same time.marcel2008-03-041-1/+1
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* Add the pic_ipi method. While here, eliminate the unused openpic_ocpbus_softcmarcel2008-03-041-9/+4
| | | | struct.
* Import the omitted gdb_machdep.c for PowerPC kernel.raj2008-03-031-2/+57
| | | | | Approved by: cognet (mentor) MFp4: e500
* Connect MPC85XX to the PowerPC build.raj2008-03-032-0/+74
| | | | | | | | | | | | | | | | | The kernel config file is KERNCONF=MPC85XX, so the usual procedure applies: 1. make buildworld TARGET_ARCH=powerpc 2. make buildkernel TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 KERNCONF=MPC85XX This default config uses kernel-level FPU emulation. For the soft-float world approach: 1. make buildworld TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 2. disable FPU_EMU option in sys/powerpc/conf/MPC85XX 3. make buildkernel TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 KERNCONF=MPC85XX Approved by: cognet (mentor) MFp4: e500
* Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.raj2008-03-0321-3/+9456
| | | | | | | | | | | | | | | | | | | | | | | | | | The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.raj2008-03-0310-139/+730
| | | | | | Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Unify and generalize PowerPC headers, adjust AIM code accordingly.raj2008-03-0212-105/+240
| | | | | | | | | | | | | | | | | | | | Rework of this area is a pre-requirement for importing e500 support (and other PowerPC core variations in the future). Mainly the following headers are refactored so that we can cover for low-level differences between various machines within PowerPC architecture: <machine/pcpu.h> <machine/pcb.h> <machine/kdb.h> <machine/hid.h> <machine/frame.h> Areas which use the above are adjusted and cleaned up. Credits for this rework go to marcel@ Approved by: cognet (mentor) MFp4: e500
* - Remove the old smp cpu topology specification with a new, more flexiblejeff2008-03-021-0/+7
| | | | | | | | | | | | | | | | | tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia
* Avoid hardcoding the kernel link address in the linker script.marcel2008-02-272-0/+7
| | | | | Use KERNBASE instead. While here, move the text sections forward to the beginning of the text segment.
* Teach PowerPC CPU identification routines to recognize e500 cores. Fix styleraj2008-02-253-93/+117
| | | | | | | issues in this area. Approved by: cognet (mentor) MFp4: e500
* Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPCraj2008-02-241-1/+5
| | | | | | | | | variations (e500 currently), this provides a gcc-level FPU emulation and is an alternative approach to the recently introduced kernel-level emulation (FPU_EMU). Approved by: cognet (mentor) MFp4: e500
* Don't define DEBUG. No debugging required.marcel2008-02-241-2/+0
| | | | Pointy hat: marcel
* Resolve warnings exposed by LINT.marcel2008-02-245-26/+5
| | | | | o Put prototypes in a single header only. o Fix printf format specifiers.
* Add FPU_EMU.marcel2008-02-231-0/+2
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* Add a floating-point emulator so that a single userland or single ABImarcel2008-02-2313-0/+3880
| | | | | | | | | | can run on processors that don't have a FPU. This is typically the case for Book E processors. While a tuned system will probably want to use soft-float (or use a processor that has a FPU if the usage is FP intensive enough), allowing hard-float on FPU-less systems gives great portability and flexibility. Obtained from: NetBSD
* Define the bootinfo structure for FreeBSD. It is not used onmarcel2008-02-232-73/+56
| | | | AIM, but it's used for BookE.
* Enable option WITNESS_SKIPSPIN by default.marcel2008-02-161-0/+1
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