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* Convert PTE eviction lock from an RW lock to a RM lock. It is held fornwhitehorn2015-03-161-16/+16
| | | | | | | writing approximately never (< 0.00000001% under heavy VM load, and it can go for months without ever being acquired in normal operation). This provides a 10% (2-minute) improvement in wall clock time for make -j32 buildworld on a 4-core 32-thread POWER8.
* Deallocate any leftover page table entries in the LPAR at boot. Thisnwhitehorn2015-03-131-0/+14
| | | | prevents contamination from a previous kernel (e.g. after shutdown -r).
* The H_VIO_SIGNAL hypercall only enables interrupts for future receivednwhitehorn2015-03-121-0/+13
| | | | | | | | | | packets and does not schedule interrupts for any packets currently enqueued. Close two races where enqueued packets may not ever trigger interrupts. The first of these, at adapter initialization time, was especially severe since a rush of enqueued packets could actually fill the receive buffer completely, stalling the interface forever. MFC after: 2 weeks
* New pmap implementation for 64-bit PowerPC processors. The main focus ofnwhitehorn2015-02-241-157/+171
| | | | | | | | | | | | | | | | | | | | | | | this change is to improve concurrency: - Drop global state stored in the shadow overflow page table (and all other global state) - Remove all global locks - Use per-PTE lock bits to allow parallel page insertion - Reconstruct state when requested for evicted PTEs instead of buffering it during overflow This drops total wall time for make buildworld on a 32-thread POWER8 system by a factor of two and system time by a factor of three, providing performance 20% better than similarly clocked Core i7 Xeons per-core. Performance on smaller SMP systems, where PMAP lock contention was not as much of an issue, is nearly unchanged. Tested on: POWER8, POWER5+, G5 UP, G5 SMP (64-bit and 32-bit kernels) Merged from: user/nwhitehorn/ppc64-pmap-rework Looked over by: jhibbits, andreast MFC after: 3 months Relnotes: yes Sponsored by: FreeBSD Foundation
* Fix race in interrupt handling that could cause IO to hang up under heavynwhitehorn2015-02-231-6/+7
| | | | load.
* Add error reporting to interrupt CPU binding.nwhitehorn2015-02-101-3/+6
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* Distribute interrupts across multiple CPUs in SMP configurations instead of ↵nwhitehorn2015-02-091-3/+15
| | | | | | sending them all to CPU 0.
* Mark invalid page table entries correctly for PMAP as well as for thenwhitehorn2015-02-091-2/+4
| | | | | | | | | | | hypervisor. This prevents an infinite loop where processes with evicted pages would page fault forever when PMAP decided the evicted pages on which the process was faulting was actually present and did not need to be restored. Found while building LLVM with make -j32. Sponsored by: FreeBSD Foundation
* Properly hide a variable under #ifdef as it is only used inside thebz2015-02-091-1/+1
| | | | | specific #ifdef block otherwise leaving an unused variable and breaking other kernel builds.
* Fix typo in PTE insertion overflow handling: use the page we're actuallynwhitehorn2015-02-091-1/+4
| | | | returning, not the one we just looked at.
* Technically speaking, using one virtal processor area for all CPUs is anwhitehorn2015-02-091-12/+20
| | | | violation of the spec. Make duplicate entries for each CPU.
* Add some error checking on the supplied page size list. This makes surenwhitehorn2015-02-081-7/+16
| | | | | | | | that we (a) get the correct large page size to provide to pmap and (b) we can alert the user if running under incorrectly-configured PowerKVM on POWER7 and POWER8 systems. MFC after: 1 week
* Fix bug in mapppings of multiple pages exposed by updates to the VSCSInwhitehorn2015-01-271-7/+7
| | | | | | | support in QEMU. Each page of a many page mapping was getting mapped to the same physical address, which is not the desired behavior. MFC after: 1 week
* Restore use of ofw_bus_intr_to_rl() in the pseries vdevice driver after fixingnwhitehorn2015-01-051-21/+5
| | | | | ofw_bus_intr_to_rl() to match the spec for unspecified interrupt-parent properties.
* Revert r272109 locally, which is not quite equivalent in how it deals withnwhitehorn2015-01-051-1/+21
| | | | | missing interrupt-parent properties. A better solution will come later, but this restores pseries in QEMU for the time being.
* Allow booting with both a real Open Firmware tree and a flattened version ofnwhitehorn2015-01-011-9/+3
| | | | | | | | the Open Firmware, as provided by petitboot, for example. Note that this is not quite complete, since RTAS instantiation still depends on callable firmware. MFC after: 2 weeks
* Replace multiple nearly-identical copies of code to walk through an FDTian2014-09-251-21/+1
| | | | | | | | | | | | | | | | node's interrupts=<...> property creating resource list entries with a single common implementation. This change makes ofw_bus_intr_to_rl() the one true copy of that code and removes the copies of it from other places. This also adds handling of the interrupts-extended property, which allows specifying multiple interrupts for a node where each interrupt can have a separate interrupt-parent. The bindings for this state that the property cells contain an xref phandle to the interrupt parent followed by whatever interrupt info that parent normally expects. This leads to having a variable number of icells per interrupt in the property. For example you could have <&intc1 1 &intc2 26 9 0 &intc3 9 4>. Differential Revision: https://reviews.freebsd.org/D803
* Mechanically convert to if_inc_counter().glebius2014-09-191-2/+2
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* Move Open Firmware device root on PowerPC, ARM, and MIPS systems tonwhitehorn2014-02-054-5/+5
| | | | | | | | a sub-node of nexus (ofwbus) rather than direct attach under nexus. This fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier. SPARC is unchanged. Reviewed by: imp, ian
* Open Firmware interrupt specifiers can consist of arbitrary-length bytenwhitehorn2014-02-011-1/+1
| | | | | | | | | strings and include arbitrary information (IRQ line/domain/sense). When the ofw_bus_map_intr() API was introduced, it assumed that, as on most systems, these were either 1 cell, containing an interrupt line, or 2, containing a line number plus a sense code. It turns out a non-negligible number of ARM systems use 3 (or even 4!) cells for interrupts, so make this more general.
* Set max_lun to zero. This field is ignored unless we are manually probingnwhitehorn2013-12-151-1/+1
| | | | | | | LUNs anyway, and we certainly don't want to probe 2^32 values by hand in that case. MFC after: 2 weeks
* Do some cosmetic fixes.andreast2013-12-051-7/+7
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* Rearchitect platform memory map parsing to make it lessnwhitehorn2013-12-011-5/+101
| | | | | | | | | | Open Firmware-centric: - Keep the static list of regions in platform.c instead of ofw_machdep.c - Move various merging and sorting operations to platform.c as well - Move apple_hacks code out of ofw_machdep.c and into platform_powermac.c, where it belongs - Move CHRP-specific dynamic-reconfiguration memory parsing into platform_chrp.c instead of pretending it is shared code
* This driver doesn't need the /options node, so don't check for it.nwhitehorn2013-11-271-3/+1
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* Take care to handle the full 16 byte buffer in the get/put routines. Also,andreast2013-11-261-8/+26
| | | | | | | skip the VTERM header once when receiving data from the hypervisor call when we have a HVTERMPROT connection. MFC after: 1 week
* Limit the large page size to 16MB for now.andreast2013-11-231-0/+5
| | | | MFC after: 1 week
* For PCI<->PCI bridges, #address-cells may be 3. Allow this when parsing thenwhitehorn2013-11-211-11/+13
| | | | | | | | ibm,dma-window properties. This is especially a concern when #ibm,dma-address-cells is not specified and we have to use the regular #address-cells property. MFC after: 1 week
* Following the approach with ACPI DMAR on x86, split IOMMU handling intonwhitehorn2013-11-122-31/+113
| | | | | | | a variant PCI bus instead of trying to shoehorn it into the PCI host bridge adapter. Besides matching better the architecture on other platforms, this also allows systems with multiple partitionable endpoints per PCI host bridge to work correctly.
* Actually add IOMMU domain to the list of known mappings. This fixes a bugnwhitehorn2013-11-121-0/+3
| | | | | | | where multiple devices in the same IOMMU domain would be allocated conflicting mappings unless they also shared a DMA tag. MFC after: 3 days
* Ouch, do the shift properly. An uin64_t needs the right postfix when shifting.andreast2013-10-311-1/+1
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* The ofw_bus() routines invoke the device's parent, not the device itself,nwhitehorn2013-10-291-3/+3
| | | | | | so cease iterating when the parent is NULL, not when the device is. MFC after: 5 days
* Implement extended LUN support. If PIM_EXTLUNS is set by a SIM, encodenwhitehorn2013-10-291-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | the upper 32-bits of the LUN, if possible, into the target_lun field as passed directly from the REPORT LUNs response. This allows extended LUN support to work for all LUNs with zeros in the lower 32-bits, which covers most addressing modes without breaking KBI. Behavior for drivers not setting PIM_EXTLUNS is unchanged. No user-facing interfaces are modified. Extended LUNs are stored with swizzled 16-bit word order so that, for devices implementing LUN addressing (like SCSI-2), the numerical representation of the LUN is identical with and without PIM_EXTLUNS. Thus setting PIM_EXTLUNS keeps most behavior, and user-facing LUN IDs, unchanged. This follows the strategy used in Solaris. A macro (CAM_EXTLUN_BYTE_SWIZZLE) is provided to transform a lun_id_t into a uint64_t ordered for the wire. This is the second part of work for full 64-bit extended LUN support and is designed to a bridge for stable/10 to the final 64-bit LUN code. The third and final part will involve widening lun_id_t to 64 bits and will not be MFCed. This third part will break the KBI but will keep the KPI unchanged so that all drivers that will care about this can be updated now and not require code changes between HEAD and stable/10. Reviewed by: scottl MFC after: 2 weeks
* - Provide necessary includes.glebius2013-10-291-2/+3
| | | | | | | - Remove unnecessary includes. Sponsored by: Netflix Sponsored by: Nginx, Inc.
* Clean up missed header references.nwhitehorn2013-10-261-1/+1
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* Add two new interfaces to ofw_bus:nwhitehorn2013-10-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | - ofw_bus_map_intr() Maps an (iparent, IRQ) tuple to a system-global interrupt number in some platform dependent way. This is meant to be implemented as a replacement for [FDT_]MAP_IRQ() that is an MI interface that knows about the bus hierarchy. - ofw_bus_config_intr() Configures an interrupt (previously mapped) based on firmware sense flags. This replaces manual interpretation of the sense field in bus drivers and will, in a follow-up, allow that interpretation to be redirected to the PIC drivers where it belongs. This will eventually replace the tables in /sys/dev/fdt/fdt_ARCH.c The PowerPC/AIM code has been converted to use these globally, with an implementation in terms of MAP_IRQ() and powerpc_config_intr(), assuming OpenPIC, at the bus root in nexus(4). The ofw_bus_config_intr() will shortly be integrated into pic_if.m and bounced through nexus into the PIC tree. FDT integration will happen significantly later due to larger testing requirements. This patch in general also lays the groundwork for the removal of /sys/dev/fdt/fdt_ARCH.c and machine/fdt.h.
* Add multicast filter control.nwhitehorn2013-10-201-5/+50
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* Clean up some debug code that snuck in. Add a block comment on future work.nwhitehorn2013-10-201-10/+9
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* Add initial driver for POWER hypervisor interpartition ethernet. This isnwhitehorn2013-10-201-0/+454
| | | | | sufficient to pass traffic but needs some more work before merging to STABLE.
* Allow hypervisor calls with more than 7 arguments.nwhitehorn2013-10-201-0/+2
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* Add driver for the PAPR VSCSI virtual SCSI controller. This lets FreeBSDnwhitehorn2013-09-282-1/+1034
| | | | | | | | | | | install directly into standard POWER LPARs, as found for example in QEMU. The core of this device is the SCSI RDMA protocol as also found in Infiniband. The SRP portions of the driver will be factored out and placed /sys/cam in the future to allow them to be used for IB storage. Thanks to Scott Long for a great deal of implementation help. Reviewed by: scottl Approved by: re (kib)
* Rework handling of ofw_quiesce(), making it the responsibility of thenwhitehorn2013-09-271-0/+3
| | | | | | | | | | platform modules. Whether to call this function or not is highly machine dependent: on some systems, it is required, while on others it breaks everything. Platform modules are in a better position to figure this out. This is required for POWER hypervisor SCSI to work correctly. There are no functional changes on Powermac systems. Approved by: re (kib)
* Make sure that ref and changed bits propagate back to the VM layernwhitehorn2013-09-271-6/+13
| | | | | | | whenever pages are unmapped. The old code had several races that could allow these to become stale. Approved by: re (kib)
* As idling the CPU no longer causes hangs on QEMU, reenable the pSeriesnwhitehorn2013-09-261-2/+0
| | | | | | cpu_idle() routine. Approved by: re (delphij)
* Fix bug where UART unit number was not set properly, which preventednwhitehorn2013-09-261-4/+1
| | | | | | | | operation on systems with multiple serial ports. Also turn on interrupts for the UART device, which were disabled due to a now-fixed bug in QEMU. Approved by: re (gjb)
* Merge in support for PAPR-compliant (Power Architecture Platformnwhitehorn2013-09-1711-0/+2840
Requirements) systems from the projects/pseries branch. This in principle includes all IBM POWER hardware released in the last 15 years with the exception of POWER3-based systems when run in 64-bit mode. The main development target, however, has been the PAPR logical partition support that is the default target in KVM on POWER and QEMU -- mileage may vary on actual hardware at present. Much of the heavy lifting here was done by Andreas Tobler. Approved by: re (kib)
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