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* Rework smu(4) to be asynchronous. It turns out that the combination ofnwhitehorn2010-03-041-73/+181
| | | | | | the automatic fan management and the polling in smu_run_cmd() was putting my system interrupt load at 20%. This change reduces that to 0.4%.
* Add the ability to set SMU-based machines to restart automatically afternwhitehorn2010-02-241-0/+58
| | | | power loss.
* Provide a new useless feature: an led(4) interface for the system's sleepnwhitehorn2010-02-221-0/+24
| | | | LED.
* Add a simple fan management callout to the SMU driver. This is designednwhitehorn2010-02-211-4/+112
| | | | | | such that a fancier thermal management algorithm can be run from user space, but the kernel will at least ensure your machine does not either sound like a wind tunnel or catch fire.
* Fix several mistakes in this file, in order to allow individual fan speedsnwhitehorn2010-02-211-19/+48
| | | | to be read and set correctly.
* Allow the SMU driver to read a variety of hardware sensors (possiblenwhitehorn2010-02-191-9/+439
| | | | | | | | questions on the thermal calibration), and to read and set fan RPMs from software. While here, fix a number of bugs. Calibration code from: OpenBSD MFC after: 2 weeks
* MFp4:mav2009-12-063-51/+33
| | | | | | | | | | | | | | | | | | Introduce ATA_CAM kernel option, turning ata(4) controller drivers into cam(4) interface modules. When enabled, this options deprecates all ata(4) peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers (ada, cd, ...) and interfaces to be natively used instead. As side effect of this, ata(4) mode setting code was completely rewritten to make controller API more strict and permit above change. While doing this, SATA revision was separated from PATA mode. It allows DMA-incapable SATA devices to operate and makes hw.ata.atapi_dma tunable work again. Also allow ata(4) controller drivers (except some specific or broken ones) to handle larger data transfers. Previous constraint of 64K was artificial and is not really required by PCI ATA BM specification or hardware. Submitted by: nwitehorn (powerpc part)
* Allow Heathrow-based machines to boot a kernel containing option SMPnwhitehorn2009-10-241-1/+7
| | | | without panicing.
* Add cpufreq support on the PowerPC G5, along with a skeleton SMU drivernwhitehorn2009-06-231-0/+288
| | | | | in order to slew CPU voltage during frequency changes. The OpenBSD SMU driver was an extremely helpful reference for this.
* strict kobj signatures: fix adb_hb_controller_poll impl in powermacavg2009-06-112-5/+7
| | | | | | | the method return u_int, not void Reviewed by: imp, current@ Approved by: jhb (mentor)
* Provide an analogous sysctl to hw.acpi.acline (dev.pmu.0.acline) tonwhitehorn2009-05-311-0/+26
| | | | determine whether the computer is plugged in to mains power.
* Introduce support for cpufreq on PowerPC with the dynamic frequencynwhitehorn2009-05-311-0/+112
| | | | switching capabilities of the MPC7447A and MPC7448.
* Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge modenwhitehorn2009-04-042-0/+683
| | | | | | | | | | provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4. This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge). Reviewed by: grehan
* Disable ATA DMA for ATAPI devices for now. Apparently, certain revisionsnwhitehorn2009-03-251-0/+4
| | | | | of this controller, in combination with certain ATAPI devices and phases of the moon, will cause DMA operations for ATAPI to fail.
* Fix a race condition in kiic(4) made possible by the way the device's STOPnwhitehorn2009-01-201-18/+17
| | | | | | | condition is sent. We used to put the bus in the STOP state, but returned without waiting for that to actually occur. Submitted by: Marco Trillo
* Provide a device description for macio-attached ATA cells.nwhitehorn2009-01-191-0/+2
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* Driver for Apple Keywest I2C controllers found in MacIO ASICs. Used fornwhitehorn2009-01-151-0/+391
| | | | | | | | power and thermal control, as well as GPIOs on Xserves and controlling sound codecs for Apple built-in audio. Submitted by: Marco Trillo Obtained from: NetBSD
* Some early Macintosh GPIO controllers don't provide reg properties fornwhitehorn2009-01-121-10/+27
| | | | | | | interrupt-only GPIOs. Honor this, and allow interrupt attachment, but not read/write access for such devices. Reported by: Niels Eliasen
* Add a new quirk type so that the MacIO driver will assign memory resourcesnwhitehorn2009-01-061-2/+8
| | | | | | | | belonging to a devices children, in analogy to the way we handle interrupts for SCC serial devices. This is required to counteract overly deep nesting on onboard audio devices. Submitted by: Marco Trillo
* Fix the OFW interrupt map parser to use its own idea of the number of interruptnwhitehorn2009-01-035-31/+11
| | | | | | | | | cells in the map, instead of using a value passed to it and then panicing if it disagrees. This fixes interrupt map parsing for PCI bridges on some Apple Uninorth PCI controllers. Reported by: marcel Tested on: G4 iBook, Sun Ultra 5
* Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,nwhitehorn2008-12-155-5/+65
| | | | | | | | | | | | | | | the code for parsing interrupt maps) to PowerPC and reflect their new MI status by moving them to the shared dev/ofw directory. This commit also modifies the OFW PCI enumeration procedure on PowerPC to allow the bus to find non-firmware-enumerated devices that Apple likes to add, and adds some useful Open Firmware properties (compat and name) to the pnpinfo string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the change to PCI enumeration on PowerPC, X has started working again on PPC machines with Grackle hostbridges. Reviewed by: marius Obtained from: sparc64
* Use a static free packet queue instead of using malloc() to allocate new ADB ↵nwhitehorn2008-12-132-13/+28
| | | | | | packets. This fixes some locking problems.
* Add the ability to control the sleep LED with led(4). Adding this fairlynwhitehorn2008-12-092-5/+29
| | | | useless feature gives us a reasonably complete PMU implementation.
* Clean up the mac GPIO interface a little. Also remove bogus copyrightnwhitehorn2008-12-082-26/+29
| | | | | | and 3rd license clause. Submitted by: Marco Trillo
* Add facilities to pmu(4) to interrogate battery status on Apple PowerPCnwhitehorn2008-12-082-12/+219
| | | | | | laptops. This includes battery presence detection, charging status, current and voltage readouts, and charge level indication. The sysctl interface is somewhat ACPI-like.
* Add support for automated reboot after power failure on Apple Core99 machinesnwhitehorn2008-12-071-3/+61
| | | | | (G3 laptops, all G4 machines, early G5s, G5 Xserves). The relevant sysctl is named dev.pmu.0.server_mode for mental compatibility with Linux.
* Fix some nasty race conditions in the VIA-CUDA driver that ended up preventingnwhitehorn2008-12-062-90/+175
| | | | | | my right mouse button and keyboard LEDs from working due to mangled configuration packets. Fixed several other races and associated problems in the main ADB stack that were exposed while fixing this.
* Fix some possible infinite loops in the ADB code, and remove some hacksnwhitehorn2008-10-302-21/+9
| | | | | that were inserted in desperation during bring-up. In addition, move ADB bus enumeration and child attachment to when interrupts are available.
* DBDMA can transfer a maximum of 64K - 1 bytes per descriptor, as the bytenwhitehorn2008-10-281-0/+6
| | | | | | count field is 16 bits. Inform ATA of this fact. Reported by: Marco Trillo
* Clean up some magic numbers in the DBDMA code by replacing them withnwhitehorn2008-10-272-11/+20
| | | | | | appropriately defined constants. Suggested by: gnn
* Bring Kauai ATA driver in line with Macio ATA by reading the PIO config regnwhitehorn2008-10-271-6/+2
| | | | | | | | | | | | to set the initial PIO mode instead of assuming PIO4. There are still a few nagging issues: - There are some problems with 64 K DMA transfers waiting on lower level changes. - ATAPI DMA is broken on Marcel's Mac Mini because we need an ATA SELECT hook propagated up to individual drivers for hardware without timing registers for each ATA channel.
* Add ADB support. This provides support for the external ADB bus on the PowerMacnwhitehorn2008-10-268-0/+1961
| | | | | | | | G3 as well as the internal ADB keyboard and mice in PowerBooks and iBooks. This also brings in Mac GPIO support, for which we should eventually have a better interface. Obtained from: NetBSD (CUDA and PMU drivers)
* Convert PowerPC AIM PCI and nexus busses to standard OFW bus interface. Thisnwhitehorn2008-10-147-90/+125
| | | | | | | | | | | simplifies certain device attachments (Kauai ATA, for instance), and makes possible others on new hardware. On G5 systems, there are several otherwise standard PCI devices (Serverworks SATA) that will not allow their interrupt properties to be written, so this information must be supplied directly from Open Firmware. Obtained from: sparc64
* Expand the DBDMA API to allow setting device-dependent control bits. Whilenwhitehorn2008-09-271-2/+20
| | | | | | | here, clean up and document this a little. Submitted by: Marco Trillo MFC after: 1 week
* Add DMA support for Apple built-in ATA controllers.nwhitehorn2008-09-274-34/+795
| | | | | Tested by: grehan, marcotrillo@gmail.com MFC after: 1 month
* Change the DBDMA API to allow DBDMA registers in a subregion of a resource. ↵nwhitehorn2008-09-232-8/+11
| | | | | | This is necessary to allow future support of DMA for the various Apple on-board ATA controllers. MFC after: 1 week
* Return an error code rather than ENXIO when both rman_init() andkevlo2008-06-123-28/+33
| | | | | | rman_manage_region() failed. Reviewed by: marcel
* Add support for Apple's Descriptor-Based DMA (DBDMA) engine. The DMAmarcel2008-06-072-0/+433
| | | | | | | engine is usful to various existing drivers, such as ata(4) and scc(4), and is used bhy the soon to be added bm(4). Submitted by: Nathan Whitehorn
* Take into account the size of the interrupt cell. It's determinedmarcel2008-04-262-14/+27
| | | | | | | | | | | by the parent for interrupt resources. This corrects parsing of the interrupts property. With parsing of the property fixed, add all interrupts to the resource list. Bump the max. number of interrupts from 5 to 6 as scc(4) attached to macio(4) has 6 interrupts (3 per channel). Submitted by: Nathan Whitehorn <nathanw@uchicago.edu>
* Add support for the BUS_CONFIG_INTR() method to the platform and tomarcel2008-03-071-0/+1
| | | | | openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
* Add PIC support for IPIs. When registering an interrupt handler,marcel2008-02-122-1/+10
| | | | | | the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
* One of my powerbooks has this chip in it..julian2008-01-261-0/+1
| | | | | | Confirmed by looking at netbsd.. they have also added this. checked by grehen MFC After: 3 days
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-251-1/+1
| | | | | | | | | for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run. Assign approximate why values to all current consumers of the kdb_enter() interface.
* Apply missing s/rv/res/g in previous commit.marcel2007-12-213-3/+3
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* MFamd64/ia64/i386: Only set the rman bus tags and handles injhb2007-12-203-6/+3
| | | | | | | bus_activate_resource() methods instead of splitting it up between bus_alloc_resource() and bus_activate_resource(). Glanced at by: marcel
* Redefine bus_space_tag_t on PowerPC from a 32-bit integral tomarcel2007-12-193-15/+6
| | | | | | | | | | | | | | | | | | | | | | a pointer to struct bus_space. The structure contains function pointers that do the actual bus space access. The reason for this change is that previously all bus space accesses were little endian (i.e. had an explicit byte-swap for multi-byte accesses), because all busses on Macs are little endian. The upcoming support for Book E, and in particular the E500 core, requires support for big-endian busses because all embedded peripherals are in the native byte-order. With this change, there's no distinction between I/O port space and memory mapped I/O. PowerPC doesn't have I/O port space. Busses assign tags based on the byte-order only. For that purpose, two global structures exist (bs_be_tag and bs_le_tag), of which the address can be taken to get a valid tag. Obtained from: Juniper, Semihalf
* Make the PCI code aware of PCI domains (aka PCI segments) so we canmarius2007-09-302-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
* Revamp the interrupt handling in support of INTR_FILTER. This includes:marcel2007-08-113-479/+125
| | | | | | | | | | | | | | | | | | | | | | | o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
* When writing to PCI configuration registers, don't immediatelymarcel2007-04-011-3/+0
| | | | | | | | read the same register back. It can cause hangs or machine checks in certain cases. One particular case is with bge(4) when a reset is initiated for the controller. MFC after: 1 month
* Make pswitch_intr() returns interrupt handling status.piso2007-03-021-2/+3
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