summaryrefslogtreecommitdiffstats
path: root/sys/powerpc/mpc85xx
Commit message (Collapse)AuthorAgeFilesLines
* Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.raj2009-03-133-15/+8
| | | | Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
* Extend and improve MPC85XX Local Bus management.raj2008-12-185-69/+346
| | | | | | | | | | | | | | | | | - Make LBC resources management self-contained: introduce explicit LBC resources definition (much like the OCP), provide dedicated rman for LB mem space. - Full configuration of an LB chip select device: program LAW and BR/OR, map into KVA, handle all LB attributes (bus width, machine select, ecc, write protect etc). - Factor out LAW manipulation routines into shared code, adjust OCP area accordingly. - Other LBC fixes and clean-ups. Obtained from: Semihalf
* Minor clean up of BookE/MPC85XX: iprove naming and style(9).raj2008-12-171-6/+2
|
* Improve MPC85XX helper routines.raj2008-12-173-28/+65
| | | | | | - Move CCSR accessors to the shared MPC85XX area - Simplify SVR version subfield handling - Adjust OCP
* Add a driver for the Local Bus Controller.marcel2008-10-252-0/+368
| | | | Obtained from: Juniper Networks, Inc.
* Assign 0xff800000-0xffffffff to the LBC controller. That's wheremarcel2008-10-251-0/+4
| | | | the NOR flash lives by default.
* Remove mfsvr():marcel2008-04-272-2/+2
| | | | | | o The function is defined unconditionally but depends on SPR_SVR, which is defined conditionally. o spr.h defines mfspr() and mtspr(), which is no worse to use.
* Use RSTCR for resetting the MPC8572 (the old way does not apply).raj2008-04-262-7/+25
| | | | Obtained from: Freescale, Semihalf
* Introduce a dedicated file for MPC85xx-specific routines. Move cpu_reset()raj2008-04-261-0/+59
| | | | | there, as it's not relevant to Book-E specification, but is an implementation detail, directly dependent on the given SoC version.
* Improve handling of Local Access Windows on MPC85xx systems:raj2008-04-263-19/+39
| | | | | | | | - detect number of LAWs in run time and initalize accordingly - introduce decode windows target IDs used in MPC8572 - other minor updates Obtained from: Freescale, Semihalf
* Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on whatraj2008-03-121-0/+9
| | | | | | | | | | | | might be currently programmed into the registers. Underlying firmware (U-Boot) would typically program MAC address into the first unit only, and others are left uninitialized. It is now possible to retrieve and program MAC address for all units properly, provided they were passed on in the bootinfo metadata. Reviewed by: imp, marcel Approved by: cognet (mentor)
* Don't use in32() and out32() when writing to the CCSRBAR. Themarcel2008-03-091-9/+26
| | | | | | in*() and out*() primitives should not be used, other than by ISA drivers. In this case they were used for memory-mapped I/O and were not even used in the spirit of the primitives.
* Add support for the BUS_CONFIG_INTR() method to the platform and tomarcel2008-03-072-0/+17
| | | | | openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
* o We don't have to keep track of the PIC, nor do we have to make suremarcel2008-03-051-28/+39
| | | | | | | it's probed first. The PowerPC platform code deals with everything. As such, probe devices in order of their location in the memory map. o Refactor the ocpbus_alloc_resource for readability and make sure we set the RID in the resource as per the new convention.
* o Various fixes related to PCI Express:marcel2008-03-051-37/+65
| | | | | | | | | | | | | | | | | | | | | | | | | - Even for the PCI Express host controller we need to use bus 0 for configuration space accesses to devices directly on the host controller's bus. - Pass the maximum number of slots to pci_ocp_init() because the caller knows how many slots the bus has. Previously a PCI or PCI-X bus underneath a PCI Express host controller would not be enumerated properly. o Pull the interrupt routing logic out of pci_ocp_init() and into its own function. The logic is not quite right and is expected to be a bit more complex. o Fix/add support for PCI domains. The PCI domain is the unit number as per other PCI host controller drivers. As such, we can use logical bus numbers again and don't have to guarantee globally unique bus numbers. Remove pci_ocp_busnr. Return the highest bus number ito the caller of pci_ocp_init() now that we don't have a global variable anymore. o BAR programming fixes: - Non-type0 headers have at most 1 BAR, not 0. - First write ~0 to the BAR in question and then read back its size. Obtained from: Juniper Networks (mostly)
* Add the pic_ipi method. While here, eliminate the unused openpic_ocpbus_softcmarcel2008-03-041-9/+4
| | | | struct.
* Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.raj2008-03-035-0/+1695
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
OpenPOWER on IntegriCloud