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* Deallocate any leftover page table entries in the LPAR at boot. Thisnwhitehorn2015-03-131-0/+3
| | | | prevents contamination from a previous kernel (e.g. after shutdown -r).
* Provide VSX context in ucontext(3) API.nwhitehorn2015-03-121-0/+2
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* The AIM DAR (data access fault address register) and Book-E DEAR registersnwhitehorn2015-03-041-3/+2
| | | | | | have the same meaning and occupy the same memory address in the trapframe courtesy of union. Avoid some pointless #ifdef by spelling them both 'DAR' in the trapframe.
* Garbage collect old function prototypes.nwhitehorn2015-03-041-6/+0
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* New pmap implementation for 64-bit PowerPC processors. The main focus ofnwhitehorn2015-02-241-4/+17
| | | | | | | | | | | | | | | | | | | | | | | this change is to improve concurrency: - Drop global state stored in the shadow overflow page table (and all other global state) - Remove all global locks - Use per-PTE lock bits to allow parallel page insertion - Reconstruct state when requested for evicted PTEs instead of buffering it during overflow This drops total wall time for make buildworld on a 32-thread POWER8 system by a factor of two and system time by a factor of three, providing performance 20% better than similarly clocked Core i7 Xeons per-core. Performance on smaller SMP systems, where PMAP lock contention was not as much of an issue, is nearly unchanged. Tested on: POWER8, POWER5+, G5 UP, G5 SMP (64-bit and 32-bit kernels) Merged from: user/nwhitehorn/ppc64-pmap-rework Looked over by: jhibbits, andreast MFC after: 3 months Relnotes: yes Sponsored by: FreeBSD Foundation
* Kernel support for the Vector-Scalar eXtension (VSX) found on the POWER7nwhitehorn2015-02-225-3/+16
| | | | | | | | | | | | | | | | and POWER8. This instruction set unifies the 32 64-bit scalar floating point registers with the 32 128-bit vector registers into a single bank of 64 128-bit registers. Kernel support mostly amounts to saving and restoring the wider version of the floating point registers and making sure that both scalar FP and vector registers are enabled once a VSX instruction is executed. get_mcontext() and friends currently cannot see the high bits, which will require a little more work. As the system compiler (GCC 4.2) does not support VSX, making use of this from userland requires either newer GCC or clang. Relnotes: yes Sponsored by: FreeBSD Foundation
* Set thread priorities on multithreaded CPUs so that threads holding anwhitehorn2015-02-101-1/+1
| | | | | spinlock are high-priority and threads waiting for a spinlock are set to low priority.
* Make 64-bit AIM trap handlers relocatable by changing all absolute branchnwhitehorn2015-01-211-1/+2
| | | | | | | | | | | instructions to call through pointers instead. In general, these are set implicitly through relocation processing. One has to be set explicitly in machdep.c, however, to fit one handler in the tiny (8 instruction) space available. Reviewed by: andreast Differential revision: D1554 Tested on: UP and SMP G5, Cell, POWER5+
* Use TOC to look up all kernel globals on powerpc64 instead of doing thenwhitehorn2015-01-181-0/+6
| | | | | | non-relocatable lis @ha, ori @l dance and hoping they are below 4 GB. MFC after: 2 months
* Refactor PowerPC (especially AIM) init sequence to be less baroque.nwhitehorn2015-01-181-0/+3
| | | | MFC after: 2 months
* Add Altivec/VMX register support to ptrace.jhibbits2015-01-142-2/+19
| | | | | MFC after: 2 weeks Relnotes: yes
* Increase default MAXTSIZ to allow execution of larger binaries.jhibbits2015-01-101-1/+1
| | | | | | | | | This allows executing static clang built with -O0. The value is configurable by a sysctl, so if one needs to clamp it down, they still can. Discussed with: nwhitehorn,emaste
* Factor out duplicated code from dumpsys() on each architecture into genericmarkj2015-01-072-12/+69
| | | | | | | | | | | | | | code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly identical and simply redefine a number of constants and helper subroutines; a generic implementation will make it easier to implement features around kernel core dumps. This change does not alter any minidump code and should have no functional impact. PR: 193873 Differential Revision: https://reviews.freebsd.org/D904 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Reviewed by: jhibbits (earlier version) Sponsored by: EMC / Isilon Storage Division
* Truncate DB_SMALL_VALUE_MAX to a much lower value.jhibbits2015-01-041-1/+1
| | | | | | | Unlike the other architectures, the PowerPC kernel is loaded under the 2GB boundary. MFC after: 2 weeks
* Resort and resize the altivec registers in the pcb. vrsave and vscr are bothjhibbits2015-01-031-3/+3
| | | | | | | 32-bit registers via the PowerPC spec. X-MFC-with: r276634 MFC after: 2 weeks
* Dump VMX registers into the userland coredump.jhibbits2015-01-031-0/+1
| | | | | Reviewed by: nwhitehorn MFC after: 2 weeks
* Add support for dtrace:fbt on modules for PowerPCjhibbits2014-11-291-0/+3
| | | | | | | | | | | | | | | | | Summary: Revert the initial FBT-with-KDB changes for trap_subr*.S, and instead use the db_trap filter function to handle dtrace trap filtering. With this, the MMU is enabled by the support code, simplifying the codepath altogether. Test Plan: Tested on my G4 PowerBook Reviewers: #powerpc, nwhitehorn Reviewed By: nwhitehorn Differential Revision: https://reviews.freebsd.org/D1207 MFC after: 3 weeks
* Revert r274772: it is not valid on MIPSemaste2014-11-252-2/+2
| | | | Reported by: sbruno
* Use canonical __PIC__ flagemaste2014-11-212-2/+2
| | | | | | | | It is automatically set when -fPIC is passed to the compiler. Reviewed by: dim, kib Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D1179
* Add arch-specific macro SFBUF_PHYS_DMAP(), which should translate thekib2014-08-201-0/+1
| | | | | | | | | | physical address of the page to direct map address, in case SFBUF_OPTIONAL_DIRECT_MAP returns true. The case of PowerPC AIM 64bit, where the page physical address is identical to the direct map address, is accidental. Reviewed by: alc Sponsored by: The FreeBSD Foundation
* Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.cglebius2014-08-052-80/+14
| | | | | | | | | | | | | | | The MD allocators were very common, however there were some minor differencies. These differencies were all consolidated in the MI allocator, under ifdefs. The defines from machine/vmparam.h turn on features required for a particular machine. For details look in the comment in sys/sf_buf.h. As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have machine/sf_buf.h, which is usually quite small. Tested by: glebius (i386), tuexen (arm32), kevlo (arm32) Reviewed by: kib Sponsored by: Netflix Sponsored by: Nginx, Inc.
* Retire PVO_EXECUTABLE. It's neither used nor set correctly.alc2014-08-011-1/+0
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* In case we ever support little-endian PowerPC (probably userland only),nwhitehorn2014-07-061-0/+12
| | | | avoid hardcoding endianness here.
* Add a new CPU id for a POWER8 variant.nwhitehorn2014-07-061-1/+2
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* Small performance optimization. Clobber only cr0, rather than the entire CR.jhibbits2014-04-112-19/+19
| | | | | Discussed with: rdivacky,nwhitehorn MFC after: 3 weeks
* Correct the SRR1 mask, it's 10-15 not 10-11.jhibbits2014-04-061-1/+1
| | | | X-MFC-with: r263464,r263752
* Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4tijl2014-04-011-1/+1
| | | | | | -fms-extensions. MFC after: 2 weeks
* Define PSL_SRR1_MASK for BOOK-E too so MPC85XX compiles again.imp2014-03-251-0/+1
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* Mask out SRR1 bits that aren't exported to the MSR.jhibbits2014-03-211-1/+3
| | | | | | | | | | This appears to fix a strange condition with X on 32-bit PowerBooks I observed, caused by one of these bits getting set in the mcontext, but not set in the thread, which may be a symptom of another problem, more difficult to diagnose. Since these bits aren't exported anyway, this change makes it more explicit that the bits aren't MSR-related in SRR1. MFC after: 3 weeks
* Update NetBSD Foundation copyrights to 2-clause BSDemaste2014-03-182-14/+0
| | | | | | | | | | | The NetBSD Foundation states "Third parties are encouraged to change the license on any files which have a 4-clause license contributed to the NetBSD Foundation to a 2-clause license." This change removes clauses 3 and 4 from copyright / license blocks that list The NetBSD Foundation as the only copyright holder. Sponsored by: The FreeBSD Foundation
* Add hwpmc(4) support for the PowerPC 970 class processors, direct events.jhibbits2014-02-012-15/+22
| | | | | | | | | | | This also fixes asserts on removal of the module for the mpc74xx. The PowerPC 970 processors have two different types of events: direct events and indirect events. Thus far only direct events are supported. I included some documentation in the driver on how indirect events work, but support is for the future. MFC after: 1 month
* Unbreak non-SMP builds. This was broken by r259284. Also, reorganize thejhibbits2014-01-312-2/+4
| | | | | | | code introduced in that revision a bit. Reviewed by: nwhitehorn MFC after: 3 weeks
* Described in the man page but not implemented. Here it comes,andreast2014-01-131-0/+37
| | | | | | atomic_swap_32/64. The latter only for powerpc64. MFC after: 1 month
* Retire machine/fdt.h as a header used by MI code, as its function is nownwhitehorn2014-01-051-41/+0
| | | | | | | | | | | | | | | obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
* Set the PMC trapframe macros appropriatelyjhibbits2013-12-221-2/+2
| | | | MFC after: 2 weeks
* Add suspend/resume state saving for OpenPIC on PowerMac. It's likely thisjhibbits2013-12-212-0/+20
| | | | can be used on the others (cpcht and psim), but that has not been tested.
* Rebase the PMC indices at 1, since PMC_SOFT is at 0.jhibbits2013-12-141-2/+2
| | | | MFC after: 1 week
* Add PMU-based CPU frequency scaling. This method is used on most Titaniumjhibbits2013-12-134-1/+11
| | | | | | PowerBooks. MFC after: 1 month
* Increase PHYS_AVAIL_SZ because on pSeries machines we can have many logicalandreast2013-12-051-1/+5
| | | | | | | | | | regions which represent the total amount of memory. The size of these regions is not the physical size of the chip but it is a logical one and it is given by the OpenFirmware, it is selectable at boot time and varies between 16MB and 256MB in my case. There is an 'automatic' option which would select the size as 64MB in case you have around 16GB of RAM. To make sure we can allocate RAM with the automatic option bump this value of PHYS_AVAIL_SZ to 256.
* Remove fdtbus_bs_tag definition, which is now obsolete. The remainder ofnwhitehorn2013-12-021-8/+0
| | | | this file is also slated for future demolition.
* Rearchitect platform memory map parsing to make it lessnwhitehorn2013-12-011-1/+1
| | | | | | | | | | Open Firmware-centric: - Keep the static list of regions in platform.c instead of ofw_machdep.c - Move various merging and sorting operations to platform.c as well - Move apple_hacks code out of ofw_machdep.c and into platform_powermac.c, where it belongs - Move CHRP-specific dynamic-reconfiguration memory parsing into platform_chrp.c instead of pretending it is shared code
* Save and restore the trap vectors when doing OF calls on pSeries machines.andreast2013-11-231-0/+1
| | | | | | | | | | | It turned out that on pSeries machines the call into OF modified the trap vectors and this made further behaviour unpredictable. With this commit I'm now able to boot multi user on a network booted environment on my IntelliStation 285. This is a POWER5+ machine. Discussed with: nwhitehorn MFC after: 1 week
* Unify handling of illegal instruction faults between AIM and Book-E. Thisnwhitehorn2013-11-171-0/+2
| | | | | | | | allows FPU emulation on AIM as well as providing support for the mfpvr and lwsync instructions from userland on e500 cores. lwsync, in particular, is required for many C++ programs to work correctly. MFC after: 1 week
* Split the function of the PCB_FPU flags into two: PCB_FPU now indicates thatnwhitehorn2013-11-171-2/+3
| | | | | | | | | | | the actual FPU is enabled, while PCB_FPREGS indicates that the FPU state structure in the PCB is valid. This separation reflects the situation on FPU-less systems in which the FP state is used by the emulator but we don't actually want to try to turn on the non-existant FPU. Use this flag to save and restore FP regs properly on both AIM and Book-E. As a side effect, this sets up hard-FP and Altivec on Book-E CPUs with such abilities except for a trap handler to call enable_fpu()/enable_altivec().
* Remove a pointless #ifdef AIM. This is just PPC64 specific, includingnwhitehorn2013-11-171-3/+3
| | | | 64-bit Book-E.
* There is no reason Book-E needs to save XER and CTR on context switches.nwhitehorn2013-11-171-2/+0
| | | | | They aren't Book-E specific registers to begin with and, even if they were, are defined volatile by the ABI.
* Fix typo.jhibbits2013-11-131-1/+1
| | | | Submitted by: loos
* Increase the stack size for ppc64 from 4 pages to 8.jhibbits2013-11-131-1/+5
| | | | | | | | | I found a stack overflow when a coredump was taken onto a ZFS volume with heavy network activity. 2 DSI traps, plus one DECR trap, along with several function calls in the stack, overflowed the 4 pages. 8 page stack fixes this. Discussed with: nwhitehorn MFC after: 1 week
* Follow up r223485, which made AIM use the ABI thread pointer instead ofnwhitehorn2013-11-111-2/+0
| | | | | | | | | PCPU fields for curthread, by doing the same to Book-E. This closes some potential races switching between CPUs. As a side effect, it turns out the AIM and Book-E swtch.S implementations were the same to within a few registers, so move that to powerpc/powerpc. MFC after: 3 months
* As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In otheralc2013-11-081-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | words, every architecture is now auto-sizing the kmem arena. This revision changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and the definition of VM_KMEM_SIZE becomes optional. Replace or eliminate all existing definitions of VM_KMEM_SIZE. With auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for clarity. Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to that of setting the tunable vm.kmem_size. Whereas the macros VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set the size of the kmem arena at compile-time without that value being overridden by auto-sizing. Update the nearby comments to reflect the kmem submap being replaced by the kmem arena. Stop duplicating the auto-sizing formula in every machine- dependent vmparam.h and place it in kmeminit() where auto-sizing takes place. Reviewed by: kib (an earlier version) Sponsored by: EMC / Isilon Storage Division
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