summaryrefslogtreecommitdiffstats
path: root/sys/powerpc/include
Commit message (Collapse)AuthorAgeFilesLines
* Unify SPR defines formatting, no funtional changes.raj2012-05-261-88/+87
|
* Update HID defines for E500mc and E5500 CPU cores.raj2012-05-251-0/+53
| | | | Obtained from: Freescale, Semihalf
* Add a missing " to get closer to compiling.bz2012-05-241-1/+1
|
* Atomic operation acquire barriers also need to be isync on 64-bit systems.nwhitehorn2012-05-241-1/+1
|
* Revert isync for ILP32 to sync as per my original change that I discussedmarcel2012-05-241-4/+4
| | | | with Nathan. Leave __ATOMIC_ACQ as an isync as per Nathan.
* MFp4 bz_ipv6_fast:bz2012-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | in_cksum.h required ip.h to be included for struct ip. To be able to use some general checksum functions like in_addword() in a non-IPv4 context, limit the (also exported to user space) IPv4 specific functions to the times, when the ip.h header is present and IPVERSION is defined (to 4). We should consider more general checksum (updating) functions to also allow easier incremental checksum updates in the L3/4 stack and firewalls, as well as ponder further requirements by certain NIC drivers needing slightly different pseudo values in offloading cases. Thinking in terms of a better "library". Sponsored by: The FreeBSD Foundation Sponsored by: iXsystems Reviewed by: gnn (as part of the whole) MFC After: 3 days
* Fix physical address type to vm_paddr_t.raj2012-05-241-4/+4
|
* Fix the memory barriers for CPUs that do not like lwsync and wedge or causemarcel2012-05-241-12/+22
| | | | | | | | | | | | | | exceptions early enough during boot that the kernel will do ithe same. Use lwsync only when compiling for LP64 and revert to the more proven isync when compiling for ILP32. Note that in the end (i.e. between revision 222198 and this change) ILP32 changed from using sync to using isync. As per Nathan the isync is needed to make sure I/O accesses are properly serialized with locks and isync tends to be more effecient than sync. While here, undefine __ATOMIC_ACQ and __ATOMIC_REL at the end of the file so as not to leak their definitions. Discussed with: nwhitehorn
* Replace the list of PVOs owned by each PMAP with an RB tree. This simplifiesnwhitehorn2012-05-201-2/+5
| | | | | | | range operations like pmap_remove() and pmap_protect() as well as allowing simple operations like pmap_extract() not to involve any global state. This substantially reduces lock coverages for the global table lock and improves concurrency.
* Fix final bugs in memory barriers on PowerPC:nwhitehorn2012-05-042-6/+6
| | | | | | | | | | | | - Use isync/lwsync unconditionally for acquire/release. Use of isync guarantees a complete memory barrier, which is important for serialization of bus space accesses with mutexes on multi-processor systems. - Go back to using sync as the I/O memory barrier, which solves the same problem as above with respect to mutex release using lwsync, while not penalizing non-I/O operations like a return to sync on the atomic release operations would. - Place an acquisition barrier around thread lock acquisition in cpu_switchin().
* Add a convenience macro for the returns_twice attribute, and apply it todim2012-04-291-1/+1
| | | | | | | the prototypes of the appropriate functions (getcontext, savectx, setjmp, sigsetjmp and vfork). MFC after: 2 weeks
* Switch the default I/O memory barrier to eieio, as it should be. Thisnwhitehorn2012-04-241-5/+1
| | | | | | does not appear to cause any problems due to fixes elsewhere. MFC after: 2 months
* Fix copy-and-paste error in r230400.nwhitehorn2012-04-231-1/+1
| | | | MFC after: 3 days
* Provide a clearer split between read/write and acquire/release barriers.nwhitehorn2012-04-221-19/+24
| | | | This should really, actually be correct now.
* Correctly specify assembler constrains for synchronization instructions.nwhitehorn2012-04-221-3/+3
| | | | MFC after: 3 days
* Clarify what we are doing in r234583 a little better: eieio and isync donwhitehorn2012-04-221-15/+23
| | | | | | not provide general barriers, but only barriers in the context of the atomic sequences here. As such, make them private and keep the global *mb() routines using a variant of sync.
* On non-64-bit systems (which generally don't have lwsync), use eieio andnwhitehorn2012-04-221-0/+5
| | | | | | isync to implement read and write barriers, following Appendix B.2 of Book II of the architecture manual. This provides a 25% speed increase to fork() on the PowerPC G4.
* Use lwsync to provide memory barriers on systems that support it insteadnwhitehorn2012-04-221-20/+18
| | | | | | | | of sync (lwsync is an alternate encoding of sync on systems that do not support it, providing graceful fallback). This provides more than an order of magnitude reduction in the time required to acquire or release a mutex. MFC after: 2 months
* Remove dead code. The routines in atomic.S did not work properly anyway, andnwhitehorn2012-04-221-10/+0
| | | | | | | were everywhere unused. If we turn out to need them, they should be reimplemented. MFC after: 2 weeks
* Replace eieio; sync for creating bus-space memory barriers with sync.nwhitehorn2012-04-221-24/+30
| | | | | | | | | | | | sync performs a strict superset of the functions of eieio, so using both is redundant. While here, expand bus barriers to all bus_space operations, since many drivers do not correctly use bus_space_barrier(). In principle, we can also replace sync just with eieio, for a significant performance increase, but it remains to be seen whether any poorly-written drivers currently depend on the side effects of sync to properly function. MFC after: 1 week
* Organize some members of ucontext_t in the same order they are in thenwhitehorn2012-04-211-3/+3
| | | | | | trap frame. These are usually not used, and so this changes very little. MFC after: 5 days
* We don't need kcopy() in any of the remaining places it is used, sonwhitehorn2012-04-111-1/+0
| | | | | | remove it. MFC after: 2 weeks
* Give the kernel pmap lock a different name than user pmap locks. It hasnwhitehorn2012-04-061-2/+3
| | | | | | | (slightly) different semantics and renaming it prevents a (harmless) WITNESS warning during bootup for 32-bit kernels on 64-bit CPUs. MFC after: 5 days
* - Rename VM_MEMATTR_UNCACHED to VM_MEMATTR_WEAK_UNCACHEABLE on x86 tojhb2012-03-291-1/+0
| | | | | | | | | be less ambiguous and more clearly identify what it means. This attribute is what Intel refers to as UC-, and it's only difference relative to normal UC memory is that a WC MTRR will override a UC- PAT entry causing the memory to be treated as WC, whereas a UC PAT entry will always override the MTRR. - Remove the VM_MEMATTR_UNCACHED alias from powerpc.
* Allow multiple inclusion of trap.h. This has always been broken, butnwhitehorn2012-03-293-4/+10
| | | | until recently never caused problems.
* Add software PMC support.fabient2012-03-281-1/+2
| | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
* Add casts to __uint16_t to the __bswap16() macros on all arches whichdim2012-03-091-2/+2
| | | | | | | | | | | didn't already have them. This is because the ternary expression will return int, due to the Usual Arithmetic Conversions. Such casts are not needed for the 32 and 64 bit variants. While here, add additional parentheses around the x86 variant, to protect against unintended consequences. MFC after: 2 weeks
* Restore proper dot symbol creation for assembly files in the kernel build case.andreast2012-03-041-13/+46
| | | | | | | | | | | Without this patch we were not able to see the assembly function. Only the function descriptor was visible. - Distinguish between user-land and kernel when creating the ENTRY() point of assembly source. - Make the ENTRY() macro more readable, replace the .align directive with the gas platform independant .p2align directive. - Create an END()macro for later use to provide traceback tables on powerpc64.
* Replace the assembler macro WEAK_ALIAS with a new macro WEAK_REFERENCE whichandreast2012-02-051-2/+2
| | | | | | | | | has the same API as __weak_reference(). Give 'x' in SYS.h a more meaningful name. Tested on 32- and 64-bit PowerMac. Reviewed by: bde
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+15
| | | | Reviewed by: bde
* This commit adds profiling support for powerpc64. Now we can do applicationandreast2012-01-202-2/+23
| | | | | | | | | | | | | profiling and kernel profiling. To enable kernel profiling one has to build kgmon(8). I will enable the build once I managed to build and test powerpc (32-bit) kernels with profiling support. - add a powerpc64 PROF_PROLOGUE for _mcount. - add macros to avoid adding the PROF_PROLOGUE in certain assembly entries. - apply these macros where needed. - add size information to the MCOUNT function. MFC after: 3 weeks, together with r230291
* Add parentheses where required. Without them, `sizeof LDBL_MAX'das2012-01-201-4/+4
| | | | | is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a syntax error and should be. Thanks to bde for the examples.
* Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.das2012-01-161-1/+1
|
* Change the definition of FLT_EVAL_METHOD from 1 to 0. A value of 1 impliesdas2012-01-161-1/+1
| | | | | | that the compiler promotes floats to double precision in computations, but inspection of the output of a cross-compiler indicates that this isn't the case on powerpc.
* Rework SLB trap handling so that double-faults into an SLB trap handler arenwhitehorn2012-01-151-1/+3
| | | | | | | | | | | | | | possible, and double faults within an SLB trap handler are not. The result is that it possible to take an SLB fault at any time, on any address, for any reason, at any point in the kernel. This lets us do two important things. First, it removes the (soft) 16 GB RAM ceiling on PPC64 as well as any architectural limitations on KVA space. Second, it lets the kernel tolerate poorly designed hypervisors that have a tendency to fail to restore the SLB properly after a hypervisor context switch. MFC after: 6 weeks
* Introduce internal macros for __U/INT64_C to define the U/INT64_MAX/MINandreast2012-01-041-3/+11
| | | | | values properly. The previous definition only worked if __STDC_LIMIT_MACROS and __STDC_CONSTANT_MACROS were defined at the same time.
* Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).jhibbits2011-12-242-6/+12
| | | | | | | Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
* Replace __signed by signed.ed2011-12-131-1/+1
| | | | | The signed keyword is an integral part of the C syntax. There's no need to use __signed.
* Increase the available virtual address space for user programs on PowerPCnwhitehorn2011-12-111-7/+12
| | | | | | AIM systems to 4 GB on 32-bit systems and 2^64 bytes on 64-bit systems. VM_MAXUSER_ADDRESS remains at 2 GB on pending Book-E, pending review of an increase to 3 GB by those more familiar with Book-E.
* Keep track of PVO entries in each pmap, which allows much fasternwhitehorn2011-12-111-17/+19
| | | | | | | pmap_remove() for large sparse requests. This can prevent pmap_remove() operations on 64-bit process destruction or swapout that would take several hundred times the lifetime of the universe to complete. This behavior is largely indistinguishable from a hang.
* Use a global __pure2 function instead of a global register variable fornwhitehorn2011-11-171-4/+11
| | | | | curthread, like on x86 and sparc64. This makes the kernel somewhat more clang friendly, which doesn't support global register variables.
* People porting FreeBSD to new architectures ought not have todas2011-10-211-0/+10
| | | | | | | | | | | | | implement a deprecated FPU control interface in addition to the standard one. To make this clearer, further deprecate ieeefp.h by not declaring the function prototypes except on architectures that implement them already. Currently i386 and amd64 implement the ieeefp.h interface for compatibility, and for fp[gs]etprec(), which doesn't exist on most other hardware. Powerpc, sparc64, and ia64 partially implement it and probably shouldn't, and other architectures don't implement it at all.
* Remove unused define.kib2011-10-071-1/+0
| | | | MFC after: 1 month
* - Move the PG_UNMANAGED flag from m->flags to m->oflags, renaming the flagkib2011-08-091-2/+0
| | | | | | | | | | | | | | to VPO_UNMANAGED (and also making the flag protected by the vm object lock, instead of vm page queue lock). - Mark the fake pages with both PG_FICTITIOUS (as it is now) and VPO_UNMANAGED. As a consequence, pmap code now can use use just VPO_UNMANAGED to decide whether the page is unmanaged. Reviewed by: alc Tested by: pho (x86, previous version), marius (sparc64), marcel (arm, ia64, powerpc), ray (mips) Sponsored by: The FreeBSD Foundation Approved by: re (bz)
* Add the possibility to specify from kernel configs MAXCPU value.attilio2011-07-191-0/+2
| | | | | | | | | | This patch is going to help in cases like mips flavours where you want a more granular support on MAXCPU. No MFC is previewed for this patch. Tested by: pluknet Approved by: re (kib)
* Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)nwhitehorn2011-06-231-0/+8
| | | | | | | | | | | | | | | instead of a PCPU field for curthread. This averts a race on SMP systems with a high interrupt rate where the thread looking up the value of curthread could be preempted and migrated between obtaining the PCPU pointer and reading the value of pc_curthread, resulting in curthread being observed to be the current thread on the thread's original CPU. This played merry havoc with the system, in particular with mutexes. Many thanks to jhb for helping me work this one out. Note that Book-E is in principle susceptible to the same problem, but has not been modified yet due to lack of Book-E hardware. MFC after: 2 weeks
* MFCattilio2011-06-032-1/+62
|\
| * The POWER7 has only 32 SLB slots instead of 64, like other supportednwhitehorn2011-06-021-1/+1
| | | | | | | | | | | | 64-bit PowerPC CPUs. Add infrastructure to support variable numbers of SLB slots and move the user slot from 63 to 0, so that it is always available.
| * MFpseries:nwhitehorn2011-06-021-0/+61
| | | | | | | | | | | | | | | | | | | | Renovate and improve the AIM Open Firmware support: - Add RTAS (Run-Time Abstraction Services) support, found on all IBM systems and some Apple ones - Improve support for 32-bit real mode Open Firmware systems - Pull some more OF bits over from the AIM directory - Fix memory detection on IBM LPARs and systems with more than one /memory node (by andreast@)
| * The P4080 has 8 cores. Bump MAXCPU to 8 to match.marcel2011-05-291-1/+1
| |
OpenPOWER on IntegriCloud