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* Unify SPR defines formatting, no funtional changes.raj2012-05-261-88/+87
* Update HID defines for E500mc and E5500 CPU cores.raj2012-05-251-0/+53
* Add a missing " to get closer to compiling.bz2012-05-241-1/+1
* Atomic operation acquire barriers also need to be isync on 64-bit systems.nwhitehorn2012-05-241-1/+1
* Revert isync for ILP32 to sync as per my original change that I discussedmarcel2012-05-241-4/+4
* MFp4 bz_ipv6_fast:bz2012-05-241-0/+4
* Fix physical address type to vm_paddr_t.raj2012-05-241-4/+4
* Fix the memory barriers for CPUs that do not like lwsync and wedge or causemarcel2012-05-241-12/+22
* Replace the list of PVOs owned by each PMAP with an RB tree. This simplifiesnwhitehorn2012-05-201-2/+5
* Fix final bugs in memory barriers on PowerPC:nwhitehorn2012-05-042-6/+6
* Add a convenience macro for the returns_twice attribute, and apply it todim2012-04-291-1/+1
* Switch the default I/O memory barrier to eieio, as it should be. Thisnwhitehorn2012-04-241-5/+1
* Fix copy-and-paste error in r230400.nwhitehorn2012-04-231-1/+1
* Provide a clearer split between read/write and acquire/release barriers.nwhitehorn2012-04-221-19/+24
* Correctly specify assembler constrains for synchronization instructions.nwhitehorn2012-04-221-3/+3
* Clarify what we are doing in r234583 a little better: eieio and isync donwhitehorn2012-04-221-15/+23
* On non-64-bit systems (which generally don't have lwsync), use eieio andnwhitehorn2012-04-221-0/+5
* Use lwsync to provide memory barriers on systems that support it insteadnwhitehorn2012-04-221-20/+18
* Remove dead code. The routines in atomic.S did not work properly anyway, andnwhitehorn2012-04-221-10/+0
* Replace eieio; sync for creating bus-space memory barriers with sync.nwhitehorn2012-04-221-24/+30
* Organize some members of ucontext_t in the same order they are in thenwhitehorn2012-04-211-3/+3
* We don't need kcopy() in any of the remaining places it is used, sonwhitehorn2012-04-111-1/+0
* Give the kernel pmap lock a different name than user pmap locks. It hasnwhitehorn2012-04-061-2/+3
* - Rename VM_MEMATTR_UNCACHED to VM_MEMATTR_WEAK_UNCACHEABLE on x86 tojhb2012-03-291-1/+0
* Allow multiple inclusion of trap.h. This has always been broken, butnwhitehorn2012-03-293-4/+10
* Add software PMC support.fabient2012-03-281-1/+2
* Add casts to __uint16_t to the __bswap16() macros on all arches whichdim2012-03-091-2/+2
* Restore proper dot symbol creation for assembly files in the kernel build case.andreast2012-03-041-13/+46
* Replace the assembler macro WEAK_ALIAS with a new macro WEAK_REFERENCE whichandreast2012-02-051-2/+2
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+15
* This commit adds profiling support for powerpc64. Now we can do applicationandreast2012-01-202-2/+23
* Add parentheses where required. Without them, `sizeof LDBL_MAX'das2012-01-201-4/+4
* Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.das2012-01-161-1/+1
* Change the definition of FLT_EVAL_METHOD from 1 to 0. A value of 1 impliesdas2012-01-161-1/+1
* Rework SLB trap handling so that double-faults into an SLB trap handler arenwhitehorn2012-01-151-1/+3
* Introduce internal macros for __U/INT64_C to define the U/INT64_MAX/MINandreast2012-01-041-3/+11
* Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).jhibbits2011-12-242-6/+12
* Replace __signed by signed.ed2011-12-131-1/+1
* Increase the available virtual address space for user programs on PowerPCnwhitehorn2011-12-111-7/+12
* Keep track of PVO entries in each pmap, which allows much fasternwhitehorn2011-12-111-17/+19
* Use a global __pure2 function instead of a global register variable fornwhitehorn2011-11-171-4/+11
* People porting FreeBSD to new architectures ought not have todas2011-10-211-0/+10
* Remove unused define.kib2011-10-071-1/+0
* - Move the PG_UNMANAGED flag from m->flags to m->oflags, renaming the flagkib2011-08-091-2/+0
* Add the possibility to specify from kernel configs MAXCPU value.attilio2011-07-191-0/+2
* Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)nwhitehorn2011-06-231-0/+8
* MFCattilio2011-06-032-1/+62
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| * The POWER7 has only 32 SLB slots instead of 64, like other supportednwhitehorn2011-06-021-1/+1
| * MFpseries:nwhitehorn2011-06-021-0/+61
| * The P4080 has 8 cores. Bump MAXCPU to 8 to match.marcel2011-05-291-1/+1
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