| Commit message (Collapse) | Author | Age | Files | Lines |
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r263464,r263752,r275189:
Mask out SRR1 bits that aren't exported to the MSR.
This appears to fix a strange condition with X on 32-bit PowerBooks I
observed, caused by one of these bits getting set in the mcontext, but
not set in the thread, which is a symptom of another problem, more
difficult to diagnose. Since these bits aren't exported anyway, this
change makes it more explicit that the bits aren't MSR-related in SRR1.
r261095:
Fix 32-bit signal handling on ppc64. This was broken when the
PSL_USERSTATIC macro was changed. Since copying 64-bit srr1 into
32-bit srr1 drops the upper 32 bits, any bits set in the context were
dropped, meaning the context check fails. Since 32-bit set_context()
can't change those bits anyway, copy the ones from the current context
(td->td_frame) before calling set_context().
Approved by: re
Relnotes: yes (Affects 10-stable, but not 10.0-release)
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Increase the stack size for ppc64 from 4 pages to 8.
I found a stack overflow when a coredump was taken onto a ZFS volume with
heavy network activity. 2 DSI traps, plus one DECR trap, along with several
function calls in the stack, overflowed the 4 pages. 8 page stack fixes this.
Discussed with: nwhitehorn
Approved by: re
Relnotes: yes
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by flag). The ia64 pmap.c changes are direct commit, since ia64 is
removed on head.
MFC r269368 (by alc):
Retire PVO_EXECUTABLE.
MFC r269728:
Change pmap_enter(9) interface to take flags parameter and superpage
mapping size (currently unused).
MFC r269759 (by alc):
Update the text of a KASSERT() to reflect the changes in r269728.
MFC r269822 (by alc):
Change {_,}pmap_allocpte() so that they look for the flag
PMAP_ENTER_NOSLEEP instead of M_NOWAIT/M_WAITOK when deciding whether
to sleep on page table page allocation.
MFC r270151 (by alc):
Replace KASSERT that no PV list locks are held with a conditional
unlock.
Reviewed by: alc
Approved by: re (gjb)
Sponsored by: The FreeBSD Foundation
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As of r257209, all architectures have defined
VM_KMEM_SIZE_SCALE. In other words, every architecture is now
auto-sizing the kmem arena. This revision changes kmeminit() so
that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and
the definition of VM_KMEM_SIZE becomes optional.
Replace or eliminate all existing definitions of VM_KMEM_SIZE.
With auto-sizing enabled, VM_KMEM_SIZE effectively became an
alternate spelling for VM_KMEM_SIZE_MIN on most architectures.
Use VM_KMEM_SIZE_MIN for clarity.
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r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373,
r260374, r260375
Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs.
Correct license statements to reflect the fact that these files were all
derived from sys/arm/mv/bus_space.c.
In pmap_unmapdev(), remember the size, and use that as an argument to
kva_free(), or we'd end up always passing it a size of 0
In pmap_mapdev(), first check whether a static mapping exists,
Convert TI static device mapping to use the new arm_devmap_add_entry(),
Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy.
Eliminate use of fdt_immr_addr(), it's not needed for tegra
Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make
static device mappings.
Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
Add #include <machine/fdt.h> to a few files that used to get it via pollution
Enable the mv cesa security/crypto device by providing the required property
in the dts source, and adding the right devices to the kernel config.
Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs,
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.
Switch RPi to using arm_devmap_add_entry() to set up static device mapping.
Allow 'no static device mappings' to potentially work.
Don't try to find a static mapping before calling pmap_mapdev(), that logic
is now part of pmap_mapdev() and doesn't need to be duplicated here.
Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
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r259199, r259484, r259513, r259514, r259516
The kernel stack guard pages are only below the stack pointer, not above.
Remove unnecessary double-setting of the thread's onfault state in
copyinstr().
Open Firmware mandates that certain cross-references, in particular those
in /chosen, be ihandles. The ePAPR spec makes those cross-reference phandles,
since FDT has no concept of ihandles. Have the OF FDT CI module interpret
queries about ihandles as cross-reference phandles.
Real OF systems have an ihandle under /chosen/stdout, not a phandle. Use
the right type.
Rearchitect platform memory map parsing to make it less
Open Firmware-centric.
Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of
this file is also slated for future demolition.
Return the correct IEEE 1275 code for "nextprop".
Use the common Open Firmware PCI interrupt routing code instead of the
duplicate version in dev/fdt.
Configure interrupt sense based on device tree information.
Simplify the ofw_bus_lookup_imap() API slightly: make it allocate maskbuf
internally instead of requiring the caller to allocate it.
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Unify handling of illegal instruction faults between AIM and Book-E.
Make uart_cpu_powerpc work on both FDT and OFW systems.
Fix debug printfs in FPU_EMU to compile on powerpc64 and enable it for
powerpc64.
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Remove a pointless #ifdef AIM. This is just PPC64 specific, including
64-bit Book-E.
Make single precision floating point arithmetic actually work
Split the function of the PCB_FPU flags into two: PCB_FPU now indicates that
the actual FPU is enabled, while PCB_FPREGS indicates that the FPU state
structure in the PCB is valid.
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Rename the "bare" platform "mpc85xx"
Also turn "bare" into a truly bare platform
Move CCSR discovery into the platform module
There is no reason Book-E needs to save XER and CTR on context switches.
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r258024, r258027, r258051, r258052, r258243,
Follow up r223485, which made AIM use the ABI thread pointer instead of
PCPU fields for curthread, by doing the same to Book-E.
Use the same implementation of copyinout.c for both AIM and Book-E.
Actually add IOMMU domain to the list of known mappings.
Following the approach with ACPI DMAR on x86, split IOMMU handling into
a variant PCI bus instead of trying to shoehorn it into the PCI host bridge
adapter.
Make sure that TLB1 mappings are aligned correctly.
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Add some extra sanity checking and checks to printf format specifiers.
Try even harder to find a console before giving up.
Make devices with registers into the KVA region work reliably.
Turn on VM_KMEM_SIZE_SCALE on 32-bit as well as 64-bit PowerPC.
Return NOKEY instead of 0 if there are no more key presses queued.
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Add pmap_mapdev_attr() and pmap_kenter_attr() interfaces.
Fix concurrency issues with TLB1 updates and make pmap_kextract() search
TLB1 mappings as well
Interrelated improvements to early boot mappings:
- Remove explicit requirement that the SOC registers be found except as an
optimization (although the MPC85XX LAW drivers still require they be found
externally, which should change).
- Remove magic CCSRBAR_VA value.
- Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and
systems not in real-mode or global 1:1 maps in early boot.
- Allow pmap_mapdev() on Book-E to reissue previous addresses if the
area is already mapped. Additionally have it check all mappings, not
just the CCSR area.
Add some extra sanity checking and checks to printf format specifiers.
Bump initial TLB size. The kernel is not necessarily less than 16 MB
Handle (in a slightly ugly way) ePAPR-type loaders that just place a
device tree into r3.
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The old trap.h (then trap_aim.h) actually had trap ID codes for Book-E CPUs.
Use it universally. Book-E traps may also need revisiting due to the
introduction of fixed-offset traps and the deprecation of IVORs in POWER
ISA 2.06, but that's very much an issue for another day.
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Remove dead and duplicated code.
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Add two new interfaces to ofw_bus:
- ofw_bus_map_intr()
Maps an (iparent, IRQ) tuple to a system-global interrupt number in some
platform dependent way. This is meant to be implemented as a replacement
for [FDT_]MAP_IRQ() that is an MI interface that knows about the bus
hierarchy.
- ofw_bus_config_intr()
Configures an interrupt (previously mapped) based on firmware sense flags.
This replaces manual interpretation of the sense field in bus drivers and
will, in a follow-up, allow that interpretation to be redirected to the PIC
drivers where it belongs. This will eventually replace the tables in
/sys/dev/fdt/fdt_ARCH.c
The PowerPC/AIM code has been converted to use these globally, with an
implementation in terms of MAP_IRQ() and powerpc_config_intr(), assuming
OpenPIC, at the bus root in nexus(4). The ofw_bus_config_intr() will shortly
be integrated into pic_if.m and bounced through nexus into the PIC tree.
Factor out MI portions of the PowerPC nexus device into /sys/dev/ofw. The
sparc64 driver will be modified to use this shortly.
Allow PIC drivers to translate firmware sense codes for themselves. This
is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not
happen quite yet.
Do not map IRQs twice. This fixes PowerPC/FDT systems with multiple PICs,
which would try to treat the previously-mapped interrupts from
fdt_decode_intr() as interrupt line numbers on the same parent PIC.
Remove some of the code required for supporting ssm(4) on SPARC in favor
of a more PowerPC/FDT-focused design. Whenever SPARC64 is integrated
into this rework, this should be (trivially) revisited.
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Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.
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r260607:
The onyx codec works also as module, so add it.
r260610:
Described in the man page but not implemented. Here it comes,
atomic_swap_32/64. The latter only for powerpc64.
r260934:
Fix the resource information for the i2s-a node on certain G5 PowerMacs.
This is the first step needed to get the snapper codec working on those
machines.
The second step is to enable the corresponding I2S device and its clock.
Tested on machines where the snapper codec was already working, a G4 PowerBook
and a PowerMac9,1 with a Shasta based macio.
The PowerMac7,2/7,3 with a K2 based macio can now also play sound.
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The NetBSD Foundation states "Third parties are encouraged to change the
license on any files which have a 4-clause license contributed to the
NetBSD Foundation to a 2-clause license."
This change removes clauses 3 and 4 from copyright / license blocks that
list The NetBSD Foundation as the only copyright holder.
Sponsored by: The FreeBSD Foundation
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Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.
The PowerPC 970 processors have two different types of events: direct events
and indirect events. Thus far only direct events are supported. I included
some documentation in the driver on how indirect events work, but support is
for the future.
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Unbreak non-SMP builds. This was broken by r259284. Also, reorganize the
code introduced in that revision a bit.
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Add PMU-based CPU frequency scalling. This is used on most Titanium
PowerBooks.
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r259394:
Rebase the PMC indices at 1, since PMC_SOFT is at 0.
r259395,r259699:
Add userland PMC backtracing, and use the PMC trapframe macros for kernel
backtraces.
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r257991:
Consolidate Apple firmware hacks and improve them by switching on the
presence of mac-io devices in the tree, which uniquely identifies Apple
hardware.
r257992:
Allow OF_decode_addr() to also be able to map resources on big-endian
devices. To this end, make PCI device detection rely on the device_type
field rather than name, as per the standard.
r257993:
Make tsec work with the device tree present on the RB800. The previous code
assumed that the MDIO bus was a direct child of the Ethernet interface. It
may not be and indeed on many device trees is not. While here, add proper
locking for MII transactions, which may be on a bus shared by several MACs.
r258504:
Save and restore the trap vectors when doing OF calls on pSeries machines.
It turned out that on pSeries machines the call into OF modified the trap
vectors and this made further behaviour unpredictable.
With this commit I'm now able to boot multi user on a network booted
environment on my IntelliStation 285. This is a POWER5+ machine.
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Increase PHYS_AVAIL_SZ because on pSeries machines we can have many logical
regions which represent the total amount of memory. The size of these regions
is not the physical size of the chip but it is a logical one and it is given
by the OpenFirmware, it is selectable at boot time and varies between 16MB and
256MB in my case. There is an 'automatic' option which would select the size as
64MB in case you have around 16GB of RAM.
To make sure we can allocate RAM with the automatic option bump this value
of PHYS_AVAIL_SZ to 256.
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to that on x86 and sparc64.
Approved by: re (kib)
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platform modules. Whether to call this function or not is highly machine
dependent: on some systems, it is required, while on others it breaks
everything. Platform modules are in a better position to figure this
out. This is required for POWER hypervisor SCSI to work correctly. There
are no functional changes on Powermac systems.
Approved by: re (kib)
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Approved by: re (kib)
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Approved by: re (kib)
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BSP -- so that platform modules have a chance to add the new CPU to any
internal bookkeeping.
Approved by: re (kib)
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interactions with certain kinds of hypervisors that look into the PTEs
more closely than they should.
Approved by: re (kib)
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to MD headers.
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making sure they are all misaligned at +8 bytes. This fixes clang builds
of powerpc64 kernels (aside from a required increase in KSTACK_PAGES which
will come later).
This commit from FreeBSD/powerpc64 with a clang-built kernel.
MFC after: 2 weeks
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redefining them if gcc provides them.
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will likely be done as more drivers are added, since AIM-compatible processors
have similar PMC configuration logic.
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MFC after: 3 days
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This WIP should not have been committed yet.
Pointyhat to: avg
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no userland-serviceable parts inside
MFC after: 20 days
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Issues were noted by Bruce Evans and are present on all architectures.
On i386, a counter fetch should use atomic read of 64bit value,
otherwise carry from the increment on other CPU could be lost for the
given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not
available on the machine, it cannot be SMP and it is enough to disable
preemption around read to avoid the split read.
On x86 the counter increment is not atomic on purpose, which makes it
possible for the store of the incremented result to override just
zeroed per-cpu slot. The effect would be a counter going off by
arbitrary value after zeroing. Perform the counter zeroing on the
same processor which does the increments, making the operations
mutually exclusive. On i386, same as for the fetching, if the
cmpxchg8b is not available, machine is not SMP and we disable
preemption for zeroing.
PowerPC64 is treated the same as amd64.
For other architectures, the changes made to allow the compilation to
succeed, without fixing the issues with zeroing or fetching. It
should be possible to handle them by using the 64bit loads and stores
atomic WRT preemption (assuming the architectures also converted from
using critical sections to proper asm). If architecture does not
provide the facility, using global (spin) mutex would be non-optimal
but working solution.
Noted by: bde
Sponsored by: The FreeBSD Foundation
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branch import.
PR: ports/179173,ports/179164
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protocol.
Obtained from: Juniper Networks, Inc.
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order to match the MAXCPU concept. The change should also be useful
for consolidation and consistency.
Sponsored by: EMC / Isilon storage division
Obtained from: jeff
Reviewed by: alc
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as CTASSERT in MI pcpu.h, stop including all possible mutually exclusive
PCPU_MD_FIELDS fields into LINT kernels, due to brekaing
aforementioned CTASSERT.
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Introduce counter(9) API, that implements fast and raceless counters,
provided (but not limited to) for gathering of statistical data.
See http://lists.freebsd.org/pipermail/freebsd-arch/2013-April/014204.html
for more details.
In collaboration with: kib
Reviewed by: luigi
Tested by: ae, ray
Sponsored by: Nginx, Inc.
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Pad struct pcpu so that its size is denominator of PAGE_SIZE. This
is done to reduce memory waste in UMA_PCPU_ZONE zones.
Sponsored by: Nginx, Inc.
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platforms, as well as putting it in an #ifdef KERNEL block.
MFC after: 2 weeks
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