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* Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)nwhitehorn2011-06-231-1/+1
| | | | | | | | | | | | | | | instead of a PCPU field for curthread. This averts a race on SMP systems with a high interrupt rate where the thread looking up the value of curthread could be preempted and migrated between obtaining the PCPU pointer and reading the value of pc_curthread, resulting in curthread being observed to be the current thread on the thread's original CPU. This played merry havoc with the system, in particular with mutexes. Many thanks to jhb for helping me work this one out. Note that Book-E is in principle susceptible to the same problem, but has not been modified yet due to lack of Book-E hardware. MFC after: 2 weeks
* Update PowerPC event timer code to use new event timers infrastructure.mav2010-09-111-0/+4
| | | | | | Reviewed by: nwitehorn Tested by: andreast H/W donated by: Gheorghe Ardelean
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-181-1/+1
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Enable power management for E500 cores. Use "doze" for now to makemarcel2010-03-231-0/+2
| | | | | | | | sure the caches remain coherent. For single-core configurations and with busdma changes we could eventually switch to "nap" and force a D-cache invalidation as part of the DMA completion. To this end, clear PSL_WE until after we handled the decrementer or external interrupt as it tells us whether we just woke up or not.
* Place interrupt handling in a critical section and remove doublenwhitehorn2010-03-091-4/+4
| | | | | | | | | | | counting in incrementing the interrupt nesting level. This fixes a number of bugs in which the interrupt thread could be preempted by an IPI, indefinitely delaying acknowledgement of the interrupt to the PIC, causing interrupt starvation and hangs. Reported by: linimon Reviewed by: marcel, jhb MFC after: 1 week
* Minor clean up of BookE/MPC85XX: iprove naming and style(9).raj2008-12-171-1/+0
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* Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.raj2008-03-031-0/+139
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
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