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* The first argument of dcbz interprets r0 as a literal zero, not the second.nwhitehorn2009-12-031-1/+1
* Add a CPU features framework on PowerPC and simplify CPU setup a littlenwhitehorn2009-11-282-4/+8
* Simplify the invocation of vm_fault(). Specifically, eliminate the flagalc2009-11-271-3/+1
* Garbage collect some code that was never compiled in to handle Altivecnwhitehorn2009-11-221-6/+0
* Provide a real fix to the too-many-translations problem when bootingnwhitehorn2009-11-121-56/+62
* Extract the code that records syscall results in the frame into MDkib2009-11-102-37/+57
* Spell sz correctly.nwhitehorn2009-11-091-1/+1
* Increase the size of the OFW translations buffer to handle G5 systemsnwhitehorn2009-11-091-1/+4
* Unbreak cpu_switch(). The register allocator in my brain is clearlynwhitehorn2009-10-311-4/+6
* Remove an unnecessary sync that crept in the last commit.nwhitehorn2009-10-311-1/+0
* Fix a race in casuword() exposed by csup. casuword() non-atomically readnwhitehorn2009-10-311-2/+13
* Loop on blocked threads when using ULE scheduler, removing annwhitehorn2009-10-311-9/+21
* Garbage collect set_user_sr(), which is declared static inline andnwhitehorn2009-10-311-9/+0
* Turn off Altivec data-stream prefetching before going into power-savenwhitehorn2009-10-291-3/+21
* In r197963, a race with thread being selected for signal deliverykib2009-10-271-7/+1
* Remove debugging printf that snuck in here.nwhitehorn2009-10-231-1/+0
* Add some more paranoia to setting HID registers, and update the AIMnwhitehorn2009-10-233-12/+27
* Do not map the trap vectors into the kernel's address space. They arenwhitehorn2009-10-232-6/+13
* Add SMP support on U3-based G5 systems. This does not yet work perfectly:nwhitehorn2009-10-233-78/+184
* o Introduce vm_sync_icache() for making the I-cache coherent withmarcel2009-10-212-24/+60
* Don't assume that physical addresses are identity mapped. This allowsnwhitehorn2009-10-181-1/+8
* Correct another typo. Actually save the condition register insteadnwhitehorn2009-10-111-1/+1
* Correct a typo here and actually save DSISR instead of overwriting it.nwhitehorn2009-10-111-1/+1
* Increase the size of the page table on 64-bit PowerPC machines as anwhitehorn2009-07-121-2/+0
* Implement a facility for dynamic per-cpu variables.jeff2009-06-232-0/+30
* Get the gdb/psim emulator functioning again.grehan2009-06-102-6/+26
* Introduce support for cpufreq on PowerPC with the dynamic frequencynwhitehorn2009-05-311-8/+0
* Add cpu_flush_dcache() for use after non-DMA based I/O so that amarcel2009-05-181-0/+10
* PowerPC common SMP startup and time base rework.raj2009-05-141-11/+8
* Factor out platform dependent things unrelated to device drivers into anwhitehorn2009-05-148-157/+269
* Zero PCB during early AIM PowerPC init.raj2009-04-241-0/+1
* Fix a typo in the SRR1 comparison for program exceptions. While here,nwhitehorn2009-04-191-3/+2
* Changing the overflow trap to use bla to branch to dbtrap in r190946 wasnwhitehorn2009-04-141-1/+1
* Rework the way we get the cacheline size. Instead of having a table ofnwhitehorn2009-04-121-13/+38
* Fix recognition of kernel-mode traps that pass through the KDB trap handlernwhitehorn2009-04-111-4/+2
* Fix the build when KDB is disabled. The second instance of rfi innwhitehorn2009-04-051-0/+3
* Perform a dummy stwcx. when we switch contexts. The contextmarcel2009-04-041-0/+6
* Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge modenwhitehorn2009-04-049-172/+2879
* Change the PVO zone for fictitious pages to the unmanaged PVO zone, to matchnwhitehorn2009-03-111-1/+4
* Fix comment: we write the trap vector to SPRG3, not SPRG0.nwhitehorn2009-02-231-3/+3
* Add Altivec support for supported CPUs. This is derived from the FPU supportnwhitehorn2009-02-204-54/+130
* Modularize the Open Firmware client interface to allow run-time switchingnwhitehorn2008-12-203-16/+54
* Add support for kernel profiling for both AIM and BookE.marcel2008-10-271-1/+4
* Convert PowerPC AIM PCI and nexus busses to standard OFW bus interface. Thisnwhitehorn2008-10-142-3/+9
* Allow the cacheline size on PowerPC to be set at runtime. This is essential fornwhitehorn2008-09-241-4/+4
* In preparation for PowerPC G5 support, allow PVO objects to contain pagenwhitehorn2008-09-231-52/+54
* o When not making a translation cache-inhibit and guarded (PTE_I|PTE_G)marcel2008-09-161-40/+42
* Rewrite cpudep_ap_bootstrap(). We now enable L3, L2, L1D and L1Imarcel2008-09-161-14/+110
* o In decr_get_timecount() only read the low timebase register.marcel2008-09-161-4/+9
* Set pcpup->pc_curthread and pcpup->pc_curpcb before callingmarcel2008-09-161-3/+3
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