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* Killed a gratuitous assignment in a NetBSD case.dg1997-09-301-5/+1
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* Two changes which should make the system less suseptible to receiverdg1997-09-301-29/+29
| | | | | | | overruns (not that it was a problem, but it could be): 1) Doubled the number of receive buffers in the DMA chain to 64. 2) Do packet receive processing before transmit in the interrupt routine.
* Work around a bug in the 82557 NIC where the receiver will lock updg1997-09-293-57/+198
| | | | | | | | | | | | | | | | | | | | | | | if it is in 10Mbps mode and gets certain types of garbage prior to the packet header. The work-around involves reprogramming the multicast filter if nothing is received in some number of seconds (currently set at 15). As a side effect, implemented complete support for multicasting rather than the previous 'receive all multicasts' hack, since we now have the ability to program the filter table. Fixed a serious bug which crept in with the timeout() changes; the cookie was only saved on the first timeout() call in fxp_init() and wasn't updated in the most common place in fxp_stats_update() when the timeout was rescheduled. This bug would have resulted in an eventual panic if fxp_stop() was called (which happens when any interface flags are changed, for example). Fixed a bug in Alpha support that would have caused the TxCB descriptor chain to span a page boundry, causing serious problems if the pages didn't happen to be contiguous. Removed some gratuitous bit masking that was left over from an older implementation. Fixed a bug where too much was copied from the configuration template, spilling over into memory that followed it. Fixed handling of if_timer...it was cleared too early in some cases.
* Remove the 82371 IDE devices.phk1997-09-241-17/+4
| | | | | Add Intel 82439TX System Controller (MTXC) fix a whitespace problem.
* Update for new callout interface.gibbs1997-09-215-11/+15
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* Addition of support of the slightly rogue Promise IDE interface(Dyson), supportdyson1997-09-202-611/+1090
| | | | | | | | | | | of multiple PCI IDE controllers(Dyson), and some updates and cleanups from John Hood, who originally made our IDE DMA stuff work :-). I have run tests with 7 IDE drives connected to my system, all in DMA mode, with no errors. Modulo any bugs, this stuff makes IDE look really good (within it's limitations.) Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
* ``oops''. I cut/pasted the original free()'s based on mark's suggestionpeter1997-09-201-4/+4
| | | | | | | | rather than extracting the diff from Mark's patch, but it turns out that I was freeing one allocation twice due to a previous cut/paste braino. My botch, not Mark's. Pointed out by: Mark Valentine <mv@pobox.com>
* Missed a place where the extra descriptor buffers would need to bepeter1997-09-181-1/+3
| | | | | | freed. Submitted by: Mark Valentine <mark@linus.demon.co.uk>
* Update select -> poll in drivers.peter1997-09-141-2/+2
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* malloc() the rx and tx descriptors seperately rather than as part of thepeter1997-09-112-2/+17
| | | | | | | | | | | | | | | | | | large (over 4KB) softc struct. The descriptor array is accessed by busmaster dma and must be physically contiguous in memory. malloc() of a block greater than a page is only virtually contiguous, and not necessarily physically contigious. contigmalloc() could do this, but that is a bit on the overkill side. I'm not sure of the origins of the problem report and diagnosis, I learned of the problem via mail forwarded from Jim Shankland <jas@flyingfox.com>. Jim said that Matt Thomas's workaround was to reduce the number of transmit descriptors from 128 to 32, but I was concerned that it might cost performance. Anyway, this change is my fault, not Jim's. :-) Reviewed by: davidg
* Treat "reservation conflict" status similar to "busy".se1997-09-101-4/+6
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* Remove scaling of tp->period, since the value is assumed to be inse1997-09-091-12/+2
| | | | tenth of a nanoseconds by ncrcontrol
* Amancio's latest in the Brooktree driver.markm1997-09-093-238/+349
| | | | | This fixes the european frequency set, separates this further from the Meteor driver and fixes bugs.
* Changes to support NetBSD and the new ifmedia extensions.dg1997-09-053-243/+842
| | | | Submitted by: Jason Thorpe <thorpej@netbsd.org>
* Upgrade of EIDE DMA support, Johns comments:sos1997-09-041-245/+387
| | | | | | | | | | | | * lots of fixes to error handling-- mostly works now * improve DMA timing config for Triton chipsets-- PIIX4 and UDMA drive still untested * generally improve DMA config in many ways-- mostly cleanup * clean up boot-time messages * rewrite PRD generation algorithm * first wd timeout is now longer, to handle drive spinup Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
* No longer needed, superceded by ide-pci.c ide-pcireg.hsos1997-09-042-382/+0
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* Removed unused #includes.bde1997-09-025-35/+3
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* Added used #include - don't depend on <sys/mbuf.h> includingbde1997-09-021-0/+1
| | | | <sys/malloc.h> (unless we only use the bogusly shared M*WAIT flags).
* Prepare for 64bit programming environment (e.g. Alpha):se1997-08-312-45/+45
| | | | | | Use "ncrcmd" or "u_int32_t" instead of "u_long", where appropriate. Submitted by: Gerard Roudier <groudier@club-internet.fr>
* Remove debug printf() that had been ommited by accident.se1997-08-311-3/+2
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* Fix problem with early revision 53c825a and 53c875 chips, whichse1997-08-311-5/+3
| | | | | | | | | | | | | | | could cause a solid system lockup in the driver attach: These chips do not abort an access to the internal SRAM, when the driver set the software reset bit in the istat register. But the chip will never acknowledge the requested PCI bus transfer in the situation, causing an infinite wait and a lockout of other bus-masters. The problem has been reported for rev 0x11 of the 53c825a and rev 0x01 of the 53c875. Revisions 0x13 of the 53c825a and 0x03 of the 53c875 are known to support SRAM accesses, even in the software reset state.
* Scsi RESERVATION CONFLICT and BUSY support for Tekram scsi cards.itojun1997-08-301-0/+20
| | | | Checked with DC390. Pls mail me if you have any trouble with this patch.
* Go back to previous definition of FE_CACHE_SET, since the problemse1997-08-241-3/+2
| | | | | caused by read-multiple on the 53c810a should have been fixed by adjusting the alignment of the global header in rev 1.104 of ncr.c.
* Some cleanup and a fix for an assumed chip bug:se1997-08-231-93/+90
| | | | | | | | | | | | - Do not malloc SCRIPTS memory for those parts of the microcode that are to be loaded into the on-chip SRAM of the 53c825a or 875 ... - Modify ncr_chip_lookup to make adding new entries easier. - Disable use of on-chip SRAM for the 53c825 rev 0x10 to 0x12, since there seems to be a problem with rev 0x11, while 0x13 is known to work. (Tested by Chuck Robey <chuckr@glue.umd.edu>). This code will be merged into 2.2-stable after a few more days of testing in -current.
* Minor corrections to the code added in rev. 1.100 and 1.101:se1997-08-231-4/+4
| | | | | | | - fix features of 53c860 - correctly adjust data structure to cache line boundary (32 bytes) Submitted by: Gerard Roudier <groudier@club-internet.fr>
* Yank the casts.fsmp1997-08-212-3/+3
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* Reorder function decls alphabetically.fsmp1997-08-211-2/+2
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* Add a cast to eliminate a compiler warning.fsmp1997-08-211-1/+1
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* A few more casts and a function declaration for warning free kernel builds.fsmp1997-08-212-3/+4
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* Added frequencies for north american HRC cable.fsmp1997-08-171-2/+19
| | | | | Submitted by: Yixin Jin <yjin@rain.cs.ucla.edu> (I think) Resubmitted by: Kenneth Merry <ken@gt.ed.net>
* SMP Natoma motherboards cannot know if you are booting a UP or SMP OS. Thisdyson1997-08-161-1/+24
| | | | | | | mod makes sure that the Natoma chipset is set into the correct mode. In the case of my P6DNF, when booting a UP kernel, I see a substantial improvement in the latency of certain operations. It appears that the cache hit latency is curiously improved the most, per lat_mem_rd.
* Add the NetVin 5000 series NE2000 PCI card vendor and device IDs.danny1997-08-141-1/+2
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* Fix problem in the DC390_DefaultEEprom subroutine, which could leadse1997-08-111-3/+3
| | | | | | | | to spurious wites outside an alloccated array in the case of generic AMD SCSI cards. PR: kern/4217 Submitted by: Erik H. Moe <ehm@cris.com>
* Fix the VLSI chipset name from "Eagle" to "Eagle II".phk1997-08-101-5/+5
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* Add ID's for 5 VLSI chips. They're not very friendly, so this info wasphk1997-08-081-1/+12
| | | | | | found by taking my HP800CT apart, perusing HPs (Very good!) service manual and inference from a bad gif file I found in Finland. Sigh... But it's a nice machine :-)
* Remove two features that have been reported to cause problems withse1997-08-061-2/+3
| | | | | | | certain variants of the NCR chip from FE_CACHE_SET: FE_CLSE (enable cache-line size register) and FE_ERMP (enable read-multiple). They will be re-enabled, if a fix for the underlying problem (a restriction in the memory to memory move logic of some chips) has been implemented.
* Merge Matt's if_de.c changes in.peter1997-08-031-286/+546
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* This commit was generated by cvs2svn to compensate for changes in r27859,peter1997-08-032-8/+88
|\ | | | | | | which included commits to RCS files with non-trunk default branches.
| * Import Matt's if_de driver 970703 release. This (apparently) supportspeter1997-08-033-294/+634
| | | | | | | | some newer Cogent (Adaptec) cards and has some other internal changes.
| * Clean import of if_de.c as of 970513, if_de.c rev 1.86. This shouldpeter1997-06-221-2/+4
| | | | | | | | | | | | have optional if_media support. Obtained from: Matt Thomas via http://www.3am-software.com/
* | Removed unused #includes.bde1997-08-0211-80/+12
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* | Fix problem caused by a chunk of the previous patch having beense1997-07-291-3/+3
| | | | | | | | | | applied to the wrong source code lines (non-fatal, since it just made an auto variable become visible at the global level).
* | Add support for busmaster DMA on some PCI IDE chipsets.sos1997-07-293-1/+890
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I changed a few bits here and there, mainly renaming wd82371.c to ide_pci.c now that it's supposed to handle different chipsets. It runs on my P6 natoma board with two Maxtor drives, and also on a Fujitsu machine I have at work with an Opti chipset and a Quantum drive. Submitted by:cgull@smoke.marlboro.vt.us <John Hood> Original readme: *** WARNING *** This code has so far been tested on exactly one motherboard with two identical drives known for their good DMA support. This code, in the right circumstances, could corrupt data subtly, silently, and invisibly, in much the same way that older PCI IDE controllers do. It's ALPHA-quality code; there's one or two major gaps in my understanding of PCI IDE still. Don't use this code on any system with data that you care about; it's only good for hack boxes. Expect that any data may be silently and randomly corrupted at any moment. It's a disk driver. It has bugs. Disk drivers with bugs munch data. It's a fact of life. I also *STRONGLY* recommend getting a copy of your chipset's manual and the ATA-2 or ATA-3 spec and making sure that timing modes on your disk drives and IDE controller are being setup correctly by the BIOS-- because the driver makes only the lamest of attempts to do this just now. *** END WARNING *** that said, i happen to think the code is working pretty well... WHAT IT DOES: this code adds support to the wd driver for bus mastering PCI IDE controllers that follow the SFF-8038 standard. (all the bus mastering PCI IDE controllers i've seen so far do follow this standard.) it should provide busmastering on nearly any current P5 or P6 chipset, specifically including any Intel chipset using one of the PIIX south bridges-- this includes the '430FX, '430VX, '430HX, '430TX, '440LX, and (i think) the Orion '450GX chipsets. specific support is also included for the VIA Apollo VP-1 chipset, as it appears in the relabeled "HXPro" incarnation seen on cheap US$70 taiwanese motherboards (that's what's in my development machine). it works out of the box on controllers that do DMA mode2; if my understanding is correct, it'll probably work on Ultra-DMA33 controllers as well. it'll probably work on busmastering IDE controllers in PCI slots, too, but this is an area i am less sure about. it cuts CPU usage considerably and improves drive performance slightly. usable numbers are difficult to come by with existing benchmark tools, but experimentation on my K5-P90 system, with VIA VP-1 chipset and Quantum Fireball 1080 drives, shows that disk i/o on raw partitions imposes perhaps 5% cpu load. cpu load during filesystem i/o drops a lot, from near 100% to anywhere between 30% and 70%. (the improvement may not be as large on an Intel chipset; from what i can tell, the VIA VP-1 may not be very efficient with PCI I/O.) disk performance improves by 5% or 10% with these drives. real, visible, end-user performance improvement on a single user machine is about nil. :) a kernel compile was sped up by a whole three seconds. it *does* feel a bit better-behaved when the system is swapping heavily, but a better disk driver is not the fix for *that* problem. THE CODE: this code is a patch to wd.c and wd82371.c, and associated header files. it should be considered alpha code; more work needs to be done. wd.c has fairly clean patches to add calls to busmaster code, as implemented in wd82371.c and potentially elsewhere (one could imagine, say, a Mac having a different DMA controller). wd82371.c has been considerably reworked: the wddma interface that it presents has been changed (expect more changes), many bugs have been fixed, a new internal interface has been added for supporting different chipsets, and the PCI probe has been considerably extended. the interface between wd82371.c and wd.c is still fairly clean, but i'm not sure it's in the right place. there's a mess of issues around ATA/ATAPI that need to be sorted out, including ATAPI support, CD-ROM support, tape support, LS-120/Zip support, SFF-8038i DMA, UltraDMA, PCI IDE controllers, bus probes, buggy controllers, controller timing setup, drive timing setup, world peace and kitchen sinks. whatever happens with all this and however it gets partitioned, it is fairly clear that wd.c needs some significant rework-- probably a complete rewrite. timing setup on disk controllers is something i've entirely punted on. on my development machine, it appears that the BIOS does at least some of the necessary timing setup. i chose to restrict operation to drives that are already configured for Mode4 PIO and Mode2 multiword DMA, since the timing is essentially the same and many if not most chipsets use the same control registers for DMA and PIO timing. does anybody *know* whether BIOSes are required to do timing setup for DMA modes on drives under their care? error recovery is probably weak. early on in development, i was getting drive errors induced by bugs in the driver; i used these to flush out the worst of the bugs in the driver's error handling, but problems may remain. i haven't got a drive with bad sectors i can watch the driver flail on. complaints about how wd82371.c has been reindented will be ignored until the FreeBSD project has a real style policy, there is a mechanism for individual authors to match it (indent flags or an emacs c-mode or whatever), and it is enforced. if i'm going to use a source style i don't like, it would help if i could figure out what it *is* (style(9) is about half of a policy), and a way to reasonably duplicate it. i ended up wasting a while trying to figure out what the right thing to do was before deciding reformatting the whole thing was the worst possible thing to do, except for all the other possibilities. i have maintained wd.c's indentation; that was not too hard, fortunately. TO INSTALL: my dev box is freebsd 2.2.2 release. fortunately, wd.c is a living fossil, and has diverged very little recently. included in this tarball is a patch file, 'otherdiffs', for all files except wd82371.c, my edited wd82371.c, a patch file, 'wd82371.c-diff-exact', against the 2.2.2 dist of 82371.c, and another patch file, 'wd82371.c-diff-whitespace', generated with diff -b (ignore whitespace). most of you not using 2.2.2 will probably have to use this last patchfile with 'patch --ignore-whitespace'. apply from the kernel source tree root. as far as i can tell, this should apply cleanly on anything from -current back to 2.2.2 and probably back to 2.2.0. you, the kernel hacker, can figure out what to do from here. if you need more specific directions, you probably should not be experimenting with this code yet. to enable DMA support, set flag 0x2000 for that drive in your config file or in userconfig, as you would the 32-bit-PIO flag. the driver will then turn on DMA support if your drive and controller pass its tests. it's a bit picky, probably. on discovering DMA mode failures or disk errors or transfers that the DMA controller can't deal with, the driver will fall back to PIO, so it is wise to setup the flags as if PIO were still important. 'controller wdc0 at isa? port "IO_WD1" bio irq 14 flags 0xa0ffa0ff vector wdintr' should work with nearly any PCI IDE controller. i would *strongly* suggest booting single-user at first, and thrashing the drive a bit while it's still mounted read-only. this should be fairly safe, even if the driver goes completely out to lunch. it might save you a reinstall. one way to tell whether the driver is really using DMA is to check the interrupt count during disk i/o with vmstat; DMA mode will add an extremely low number of interrupts, as compared to even multi-sector PIO. boot -v will give you a copious register dump of timing-related info on Intel and VIAtech chipsets, as well as PIO/DMA mode information on all hard drives. refer to your ATA and chipset documentation to interpret these. WHAT I'D LIKE FROM YOU and THINGS TO TEST: reports. success reports, failure reports, any kind of reports. :) send them to cgull+ide@smoke.marlboro.vt.us. i'd also like to see the kernel messages from various BIOSes (boot -v; dmesg), along with info on the motherboard and BIOS on that machine. i'm especially interested in reports on how this code works on the various Intel chipsets, and whether the register dump works correctly. i'm also interested in hearing about other chipsets. i'm especially interested in hearing success/failure reports for PCI IDE controllers on cards, such as CMD's or Promise's new busmastering IDE controllers. UltraDMA-33 reports. interoperation with ATAPI peripherals-- FreeBSD doesn't work with my old Hitachi IDE CDROM, so i can't tell if I've broken anything. :) i'd especially like to hear how the drive copes in DMA operation on drives with bad sectors. i haven't been able to find any such yet. success/failure reports on older IDE drives with early support for DMA modes-- those introduced between 1.5 and 3 years ago, typically ranging from perhaps 400MB to 1.6GB. failure reports on operation with more than one drive would be appreciated. the driver was developed with two drives on one controller, the worst-case situation, and has been tested with one drive on each controller, but you never know... any reports of messages from the driver during normal operation, especially "reverting to PIO mode", or "dmaverify odd vaddr or length" (the DMA controller is strongly halfword oriented, and i'm curious to know if any FreeBSD usage actually needs misaligned transfers). performance reports. beware that bonnie's CPU usage reporting is useless for IDE drives; the best test i've found has been to run a program that runs a spin loop at an idle priority and reports how many iterations it manages, and even that sometimes produces numbers i don't believe. performance reports of multi-drive operation are especially interesting; my system cannot sustain full throughput on two drives on separate controllers, but that may just be a lame motherboard. THINGS I'M STILL MISSING CLUE ON: * who's responsible for configuring DMA timing modes on IDE drives? the BIOS or the driver? * is there a spec for dealing with Ultra-DMA extensions? * are there any chipsets or with bugs relating to DMA transfer that should be blacklisted? * are there any ATA interfaces that use some other kind of DMA controller in conjunction with standard ATA protocol? FINAL NOTE: after having looked at the ATA-3 spec, all i can say is, "it's ugly". *especially* electrically. the IDE bus is best modeled as an unterminated transmission line, these days. for maximum reliability, keep your IDE cables as short as possible and as few as possible. from what i can tell, most current chipsets have both IDE ports wired into a single buss, to a greater or lesser degree. using two cables means you double the length of this bus. SCSI may have its warts, but at least the basic analog design of the bus is still somewhat reasonable. IDE passed beyond the veil two years ago. --John Hood, cgull@smoke.marlboro.vt.us
* | Add support for loading the SCRIPTS microcode into the on-chip RAMse1997-07-281-598/+795
| | | | | | | | | | | | of the Symbios 53c825A, 53c875 and 53c895 SCSI chips. Submitted by: Gerard Roudier <groudier@club-internet.fr>
* | Added support for the Seeq 80c24 PHY; does nothing except disable thedg1997-07-251-1/+7
| | | | | | | | unsupported warning message for it.
* | Add Ultra-SCSI support and enable more features for advancedse1997-07-252-214/+738
| | | | | | | | | | | | Symbios/NCR SCSI chips (no-flush option, large fifo, ...). Submitted by: Gerard Roudier <groudier@club-internet.fr>
* | Assign correct chip set register dump functions to Triton II device IDs.se1997-07-181-2/+3
| | | | | | | | | | PR: i386/4092 Submitted by: Steve Bauer <sbauer@rock.sdsmt.edu>
* | Fix "unexpected phase change" interrupt handler: Do not access these1997-07-181-7/+10
| | | | | | | | | | | | | | dstat register twice, pass the value read the first time to the fixup code instead. Submitted by: Gerard Roudier <groudier@club-internet.fr>
* | Don't cast function pointers to (void *). This will cause warnings.bde1997-07-011-3/+1
| | | | | | | | | | | | | | They should be fixed when similar warnings for the general interrupt attach routines are fixed. Removed unused #include.
* | Modify my copyright notice to allow the sequencer to be used with GPLedgibbs1997-06-271-4/+11
| | | | | | | | software (aka Linux).
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