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path: root/sys/pci/if_rlreg.h
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* MFC r263957:yongari2014-04-141-1/+1
| | | | | | | | Increase the number of TX DMA segments from 32 to 35. It turned out 32 is not enough to support a full sized TSO packet. While I'm here fix a long standing bug introduced in r169632 in bce(4) where it didn't include L2 header length of TSO packet in the maximum DMA segment size calculation.
* MFC: r261531marius2014-02-231-0/+6
| | | | | | | | | - Implement the RX EARLYOFF and RXDV GATED bits as done by RealTek's Linux driver as iof version 8.037.00 for RTL8168{E-VL,EP,F,G,GU} and RTL8411B. This makes reception of packets work with the RTL8168G (HW rev. 0x4c000000) in my Shuttle DS47. - Consistently use RL_MSI_MESSAGES. In joint forces with: yongari
* MFC: r261529marius2014-02-231-12/+3
| | | | Try to make the style used here consistent.
* MFC r257306:yongari2013-11-041-0/+1
| | | | | Add preliminary support for RTL8168EP. Approved by: re (delphij)
* MFC r257305:yongari2013-11-041-0/+3
| | | | | | | | | Add preliminary support for RTL8168G, RTL8168GU and RTL8411B. RTL8168GU has two variants(GMII and MII) but it uses the same chip revision id. Driver checks PCI device id of controller and sets internal capability flag(i.e. jumbo frame and link speed down in WOL). Approved by: re (delphij)
* MFC r256828:yongari2013-11-041-0/+1
| | | | | Add preliminary support for RTL8106E PCIe FastEthernet. Approved by: re (delphij)
* r256827:yongari2013-11-041-0/+1
| | | | | | Correct MAC revision bits. Previously it always cleared bit 20 and bit 21. Approved by: re (delphij)
* Add D-Link DFE-520TX rev C1.yongari2013-01-161-0/+5
| | | | | Tested by: Ruslan Makhmatkhanov < cvs-src <> yandex dot ru > MFC After: 1 week
* Use correct Config registers for RTL8139 family. Unlike RTL8168 andyongari2012-02-251-0/+14
| | | | | | | | | | | | | RTL810x family , RTL8139 has different register map for Config registers. While here, follow the lead of re(4) in WOL configuration. - Disable WOL_UCAST and WOL_MCAST capabilities by default. - Config5 register write does not need to unlock EEPROM access on RTL8139 family but unlocking EEPROM access does not affect its operation and make it consistent with re(4). Reported by: Matt Renzelmann mjr <> cs dot wisc dot edu
* To save more power, switch to 10/100Mbps link when controller isyongari2011-11-231-0/+1
| | | | | | | | put into suspend/shutdown. Old PCI controllers performed that operation in firmware but for RTL8111C or newer controllers, it's responsibility of driver. It's not clear whether the firmware of RTL8111B still downgrades its speed to 10/100Mbps so leave it as it was.
* Make sure to stop TX MAC before freeing queued TX frames.yongari2011-11-231-16/+19
| | | | | | For RTL8111DP, check if the TX MAC is active by reading RL_GTXSTART register. For RTL8402/8168E-VL/8168F/8411, wait until TX queue is empty.
* Add preliminary support for RTL8168/8111F PCIe Gigabit ethernet.yongari2011-11-171-0/+1
| | | | H/W donated by: RealTek Semiconductor Corp.
* Add preliminary support for second generation RTL8105E PCIeyongari2011-11-171-0/+1
| | | | | | FastEthernet. H/W donated by: RealTek Semiconductor Corp.
* Disable PCIe ASPM (Active State Power Management) for allyongari2011-11-161-0/+1
| | | | | | | | | controllers. More and more RealTek controllers started to implement EEE feature. Vendor driver seems to load a kind of firmware for EEE with additional PHY fixups. It is known that the EEE feature may need ASPM support. Unfortunately there is no documentation for EEE of the controller so enabling ASPM may cause more problems.
* Add preliminary support for RTL8411 PCIe Gigabit ethernet withyongari2011-11-161-0/+1
| | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp.
* Add preliminary support for RTL8402 PCIe FastEthernet withyongari2011-11-161-0/+1
| | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp.
* - Import the common MII bitbang'ing code from NetBSD and convert drivers tomarius2011-11-011-20/+6
| | | | | | | | | | | | | | | | | | | | | | | | take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
* Add new device id of D-Link DGE-530T Rev. C controller. DGE-503Tyongari2011-07-301-0/+1
| | | | | | | | Rev A1 and B1 is supported by sk(4) but the DGE-530T Rev. C controller is re-branded RealTek 8169 controller. PR: kern/159116 Approved by: re (kib)
* Add initial support for RTL8401E PCIe Fast Ethernet.yongari2011-02-161-0/+1
| | | | PR: 154789
* Add support for RTL8105E PCIe Fast Ethernet controller. It seemsyongari2011-01-261-0/+1
| | | | | | | | | | | | | | the controller has a kind of embedded controller/memory and vendor applies a large set of magic code via undocumented PHY registers in device initialization stage. I guess it's a firmware image for the embedded controller in RTL8105E since the code is too big compared to other DSP fixups. However I have no idea what that magic code does and what's purpose of the embedded controller. Fortunately driver seems to still work without loading the firmware. While I'm here change device description of RTL810xE controller. H/W donated by: Realtek Semiconductor Corp.
* Do not use interrupt taskqueue on controllers with MSI/MSI-Xyongari2011-01-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | capability. One of reason using interrupt taskqueue in re(4) was to reduce number of TX/RX interrupts under load because re(4) controllers have no good TX/RX interrupt moderation mechanism. Basic TX interrupt moderation is done by hardware for most controllers but RX interrupt moderation through undocumented register showed poor RX performance so it was disabled in r215025. Using taskqueue to handle RX interrupt greatly reduced number of interrupts but re(4) consumed all available CPU cycles to run the taskqueue under high TX/RX network load. This can happen even with RTL810x fast ethernet controller and I believe this is not acceptable for most systems. To mitigate the issue, use one-shot timer register to moderate RX interrupts. The timer register provides programmable one-shot timer and can be used to suppress interrupt generation. The timer runs at 125MHZ on PCIe controllers so the minimum time allowed for the timer is 8ns. Data sheet says the register is 32 bits but experimentation shows only lower 13 bits are valid so maximum time that can be programmed is 65.528us. This yields theoretical maximum number of RX interrupts that could be generated per second is about 15260. Combined with TX completion interrupts re(4) shall generate less than 20k interrupts. This number is still slightly high compared to other intelligent ethernet controllers but system is very responsive even under high network load. Introduce sysctl variable dev.re.%d.int_rx_mod that controls amount of time to delay RX interrupt processing in units of us. Value 0 completely disables RX interrupt moderation. To provide old behavior for controllers that have MSI/MSI-X capability, introduce a new tunable hw.re.intr_filter. If the tunable is set to non-zero value, driver will use interrupt taskqueue. The default value of the tunable is 0. This tunable has no effect on controllers that has no MSI/MSI-X capability or if MSI/MSI-X is explicitly disabled by administrator. While I'm here cleanup interrupt setup/teardown since re(4) uses single MSI/MSI-X message at this moment.
* Remove TX taskqueue and directly invoke re_start in interrupt task.yongari2011-01-251-1/+0
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* Prefer MSI-X to MSI on controllers that support MSI-X. Allyongari2011-01-251-0/+2
| | | | | | | recent PCIe controllers(RTL8102E or later and RTL8168/8111C or later) supports either 2 or 4 MSI-X messages. Unfortunately vendor did not publicly release RSS related information yet. However switching to MSI-X is one-step forward to support RSS.
* Change model names of controller RTL_HWREV_8168_SPIN[123] to real ones.yongari2011-01-181-3/+3
| | | | | | | s/RL_HWREV_8168_SPIN1/RL_HWREV_8168B_SPIN1/g s/RL_HWREV_8168_SPIN2/RL_HWREV_8168B_SPIN2/g s/RL_HWREV_8168_SPIN3/RL_HWREV_8168B_SPIN3/g No functional changes.
* Implement initial jumbo frame support for RTL8168/8111 C/D/E PCIeyongari2011-01-171-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | GbE controllers. It seems these controllers no longer support multi-fragmented RX buffers such that driver have to allocate physically contiguous buffers. o Retire RL_FLAG_NOJUMBO flag and introduce RL_FLAG_JUMBOV2 to mark controllers that use new jumbo frame scheme. o Configure PCIe max read request size to 4096 for standard frames and reduce it to 512 for jumbo frames. o TSO/checksum offloading is not supported for jumbo frames on these controllers. Reflect it to ioctl handler and driver initialization. o Remove unused rl_stats_no_timeout in softc. o Embed a pointer to structure rl_hwrev into softc to keep track of controller MTU limitation and remove rl_hwrev in softc since that information is available through a pointer to structure rl_hwrev. Special thanks to Realtek for donating sample hardwares which made this possible. H/W donated by: Realtek Semiconductor Corp.
* Add initial support for RTL8168E/8111E-VL PCIe GbE.yongari2011-01-171-0/+1
| | | | H/W donated by: Realtek Semiconductor Corp.
* Implement TSO on RealTek RTL8168/8111 C or later controllers.yongari2011-01-101-0/+2
| | | | | | | | | | | | RealTek changed TX descriptor format for later controllers so these controllers require MSS configuration in different location of TX descriptor. TSO is enabled by default for controllers that use new descriptor format. For old controllers, TSO is still disabled by default due to broken frames under certain conditions but users can enable it. Special thanks to Hayes Wang at RealTek. MFC after: 2 weeks
* Remove standard PCI configuration space register definitions.yongari2010-11-081-35/+0
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* Remove trailing white spaces.yongari2010-11-081-7/+7
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* Consistently use tab character instead of using space character.yongari2010-11-081-500/+500
| | | | No functional changes.
* Follow the lead of vendor's interrupt moderation mechanism.yongari2010-11-081-1/+2
| | | | | | | | | | | | | | It seems RTL8169/RTL8168/RTL810xE has a kind of interrupt moderation mechanism but it is not documented at all. The magic value dramatically reduced number of interrupts without noticeable performance drops so apply it to all RTL8169/RTL8169 controllers. Vendor's FreeBSD driver also applies it to RTL810xE controllers but their Linux driver explicitly cleared the register, so do not enable interrupt moderation for RTL810xE controllers. While I'm here sort 8169 specific registers. Obtained from: RealTek FreeBSD driver
* Add simple MAC statistics counter reading support. Unfortunatelyyongari2010-11-051-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | useful counters like rl_missed_pkts is 16 bits quantity which is too small to hold meaningful information happened in a second. This means driver should frequently read these counters in order not to lose accuracy and that approach is too inefficient in driver's view. Moreover it seems there is no way to trigger an interrupt to detect counter near-full or wraparound event as well as lacking clearing the MAC counters. Another limitation of reading the counters from RealTek controllers is lack of interrupt firing at the end of DMA cycle of MAC counter read request such that driver have to poll the end of the DMA which is a time consuming process as well as inefficient. The more severe issue of the MAC counter read request is it takes too long to complete the DMA. All these limitation made maintaining MAC counters in driver impractical. For now, just provide simple sysctl interface to trigger reading the MAC counters. These counters could be used to track down driver issues. Users can read MAC counters maintained in controller with the following command. #sysctl dev.re.0.stats=1 While I'm here add check for validity of dma map and allocated memory before unloading/freeing them. Tested by: rmacklem
* Consistently use capital letters.yongari2010-04-091-2/+2
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* Add preliminary support for 8168E/8111E PCIe controller.yongari2010-04-091-0/+3
| | | | | | | While I'm here simplify device description string. Tested by: Michael Beckmann < michael <> apfel dot de > MFC after: 5 days
* Add initial support for RTL8103E PCIe fastethernet.yongari2010-01-271-0/+1
| | | | PR: kern/142974
* Add RTL8168DP/RTL8111DP device id. While I'm here append "8111D" toyongari2009-08-241-0/+1
| | | | | | | | the description of RTL8168D as RL_HWREV_8168D can be either RTL8168D or RTL8111D. PR: kern/137672 MFC after: 3 days
* Adding hardware ID for RTL810x PCIe found on HP Pavilion DV2-1022AX.avatar2009-07-141-0/+1
| | | | | Reviewed by: yongari Approved by: re (kib, kensmith)
* For RTL8139C+ controllers, have controller handle padding shortyongari2009-04-201-0/+1
| | | | | | | | | | | | | checksum offload frames. Software workaround used for broken controllers(RTL8169, RTL8168, RTL8168B) seem to cause watchdog timeouts on RTL8139C+. Introduce a new flag RL_FLAG_AUTOPAD to mark automatic padding feature of controller and set it for RTL8139C+ and controllers that use new descriptor format. This fixes watchdog timeouts seen on RTL8139C+. Reported by: Dimitri Rodis < DimitriR <> integritasystems dot com > Tested by: Dimitri Rodis < DimitriR <> integritasystems dot com >
* Allocating 2 MSI messages do not seem to work on certain controllersyongari2009-02-111-1/+1
| | | | | | | so use just 1 MSI message. This fixes regression introduced in r188381. Tested by: many
* - Add support for 8110SCe part. Some magic registers were taken fromjkim2009-01-201-4/+4
| | | | | | | Linux driver. - Swap hardware revisions for 8110S and 8169S as Linux driver claims. Reviewed by: yongari (early version)
* Retire RL_FLAG_INVMAR bit to match its comment and reality.jkim2009-01-201-1/+0
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* Sometimes RTL8168B seems to take long time to access GMII registersyongari2009-01-191-0/+1
| | | | | | | | in device attach phase. Double GMII register access timeout value to fix the issue. Reported by: wkoszek Tested by: wkoszek
* It seems that RealTek PCIe controllers require an explicit Tx pollyongari2008-12-171-0/+1
| | | | | | | | | | | | | | | | | | | command whenever Tx completion interrupt is raised. The Tx poll bit is cleared when all packets waiting to be transferred have been processed. This means the second Tx poll command can be silently ignored as the Tx poll bit could be still active while processing of previous Tx poll command is in progress. To address the issue re(4) used to invoke the Tx poll command in Tx completion handler whenever it detects there are pending packets in TxQ. However that still does not seem to completely eliminate watchdog timeouts seen on RealTek PCIe controllers. To fix the issue kick Tx poll command only after Tx completion interrupt is raised as this would indicate Tx is now idle state such that it can accept new Tx poll command again. While here apply this workaround for PCIe based controllers as other controllers does not seem to have this limitation. Tested by: Victor Balada Diaz < victor <> bsdes DOT net >
* For RTL8168C SPIN2 controllers, make sure to take the controlleryongari2008-12-171-0/+3
| | | | | | | | out of sleep mode prior to accessing to PHY. This should fix device attach failure seen on these controllers. Also enable the sleep mode when device is put into sleep state. PR: kern/123123, kern/123053
* Make WOL work on RTL8168B. This controller seems to requireyongari2008-12-111-0/+1
| | | | | | explicit command to enable Rx MAC prior to entering D3. Tested by: Cyrus Rahman <crahman <> gmail DOT com>
* Don't access undocumented register 0x82 on controllers thatyongari2008-12-111-0/+2
| | | | | | | have no such register. While here clear undocumented PHY register 0x0B for RTL8110S. Obtained from: RealTek FreeBSD driver
* Newer RealTek controllers requires setting stop request bit toyongari2008-12-111-0/+2
| | | | terminate active Tx/Rx operation.
* o Implemented miibus_statchg handler. It detects whether re(4)yongari2008-12-081-0/+1
| | | | | | | | | | | | | | | | established a valid link or not. In miibus_statchg handler add a check for established link is valid one for the controller(e.g. 1000baseT is not a valid link for fastethernet controllers.) o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers. o Added additional check to know whether we've really encountered watchdog timeouts or missed Tx completion interrupts. This change may help to track down the cause of watchdog timeouts. o In interrupt handler, removed a check for link state change interrupt. Not all controllers have the bit and re(4) did not rely on the event for a long time. In addition, re(4) didn't request the interrupt in RL_IMR register. Tested by: rpaulo
* Add 8168D support.yongari2008-12-021-0/+1
| | | | Submitted by: Andrew < andrewwtulloch <> gmail DOT com >
* Make RL_TWISTER_ENABLE a tunable/sysctl. Eliminate it as an option.imp2008-11-021-4/+1
| | | | | | Fix module build. Submitted by: Kostik Belousov
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