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* Change and clean the mutex lock interface.bmilekic2001-02-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mtx_enter(lock, type) becomes: mtx_lock(lock) for sleep locks (MTX_DEF-initialized locks) mtx_lock_spin(lock) for spin locks (MTX_SPIN-initialized) similarily, for releasing a lock, we now have: mtx_unlock(lock) for MTX_DEF and mtx_unlock_spin(lock) for MTX_SPIN. We change the caller interface for the two different types of locks because the semantics are entirely different for each case, and this makes it explicitly clear and, at the same time, it rids us of the extra `type' argument. The enter->lock and exit->unlock change has been made with the idea that we're "locking data" and not "entering locked code" in mind. Further, remove all additional "flags" previously passed to the lock acquire/release routines with the exception of two: MTX_QUIET and MTX_NOSWITCH The functionality of these flags is preserved and they can be passed to the lock/unlock routines by calling the corresponding wrappers: mtx_{lock, unlock}_flags(lock, flag(s)) and mtx_{lock, unlock}_spin_flags(lock, flag(s)) for MTX_DEF and MTX_SPIN locks, respectively. Re-inline some lock acq/rel code; in the sleep lock case, we only inline the _obtain_lock()s in order to ensure that the inlined code fits into a cache line. In the spin lock case, we inline recursion and actually only perform a function call if we need to spin. This change has been made with the idea that we generally tend to avoid spin locks and that also the spin locks that we do have and are heavily used (i.e. sched_lock) do recurse, and therefore in an effort to reduce function call overhead for some architectures (such as alpha), we inline recursion for this case. Create a new malloc type for the witness code and retire from using the M_DEV type. The new type is called M_WITNESS and is only declared if WITNESS is enabled. Begin cleaning up some machdep/mutex.h code - specifically updated the "optimized" inlined code in alpha/mutex.h and wrote MTX_LOCK_SPIN and MTX_UNLOCK_SPIN asm macros for the i386/mutex.h as we presently need those. Finally, caught up to the interface changes in all sys code. Contributors: jake, jhb, jasone (in no particular order)
* Update the probe some more to deal with 16/32 bit issues. If the chipwpaul2000-11-231-1/+1
| | | | | | | | | | is already in 32-bit mode, we need to be able to detect this and still read the chip ID code. Detecting 32-bit mode is actually a little tricky, since we want to avoid turning it on accidentally. The easiest way to do it is to just try and read the PCI subsystem ID from the bus control registers using 16-bit accesses and compare that with the value read from PCI config space. If they match, then we know we're in 16-bit mode, otherwise we assume 32-bit mode.
* First round of converting network drivers from spls to mutexes. Thiswpaul2000-10-131-0/+4
| | | | | | | | takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
* Add the card ID for the Am79c975 PCnet/FAST III card. This is a variantwpaul2000-10-051-0/+1
| | | | | | of the Am79c973 with "AlertIT Technology," whatever that is. Also mention support for the PCnet/FAST III cards in the documentation. The PCnet/FAST III chips have integrated 10/100 PHYs.
* Add support for the AMD Am79c976 PCnet/PRO controller chip. For nowwpaul2000-10-031-13/+1
| | | | | | | | | this just involves adding the chip ID to the supported list: the PCnet/PRO is compatible with the PCnet/FAST+ and friends and should "just work" with this driver. Also try to handle mbuf allocation failures in the receive handler more gracefully.
* Make pcn_miibus_readreg() latch onto the first PHY that it finds (aswpaul2000-09-221-0/+1
| | | | | | | | | a result of mii_phy_probe()) and use that rather than hardcoding a constant. The hardcoded way was too specific to the particular card I had and caused PHY probing to fail on at least one laptop with a built-in AMD chip. Reported by: rjk@grauel.com (Richard J Kuhns)
* Add a new driver for the AMD PCnet/FAST, FAST+ and Home PCI adapters.wpaul2000-09-201-0/+525
Previously, these cards were supported by the lnc driver (and they still are, but the pcn driver will claim them first), which is fine except the lnc driver runs them in 16-bit LANCE compatibility mode. The pcn driver runs these chips in 32-bit mode and uses the RX alignment feature to achieve zero-copy receive. (Which puts it in the same class as the xl, fxp and tl chipsets.) This driver is also MI, so it will work on the x86 and alpha platforms. (The lnc driver is still needed to support non-PCI cards. At some point, I'll need to newbusify it so that it too will me MI.) The Am79c978 HomePNA adapter is also supported.
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