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* MFC 261781:jhb2014-06-271-2/+2
| | | | | | Don't waste a page of KVA for the boot-time memory test on x86. For amd64, reuse the first page of the crashdumpmap as CMAP1/CADDR1. For i386, remove CMAP1/CADDR1 entirely and reuse CMAP3/CADDR3 for the memory test.
* MFC r258135: x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)emaste2013-11-251-33/+3
| | | | | | | | | | | | | | | Debuggers may need to change PSL_RF. Note that tf_eflags is already stored in the signal context during signal handling and PSL_RF previously could be modified via sigreturn, so this change should not provide any new ability to userspace. For background see the thread at: http://lists.freebsd.org/pipermail/freebsd-i386/2007-September/005910.html Reviewed by: jhb, kib Sponsored by: DARPA, AFRL Approved by: re (gjb)
* MFi386: r254619jkim2013-08-221-17/+0
| | | | | | Reimplement atomic_load_acq_64() and atomic_store_rel_64() for i386. Noticed by: tinderbox
* Replace kernel virtual address space allocation with vmem. This providesjeff2013-08-071-4/+2
| | | | | | | | | | | | | transparent layering and better fragmentation. - Normalize functions that allocate memory to use kmem_* - Those that allocate address space are named kva_* - Those that operate on maps are named kmap_* - Implement recursive allocation handling for kmem_arena in vmem. Reviewed by: alc Tested by: pho Sponsored by: EMC / Isilon Storage Division
* MFi386: revision 251039nyan2013-06-011-1/+1
| | | | Use slightly more idiomatic expression to get the address of array.
* - Correct mispellings of word resourcegabor2013-04-171-2/+2
| | | | Submitted by: Christoph Mallon <christoph.mallon@gmx.de>
* MFCattilio2013-03-021-6/+7
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| * MFcalloutng:davide2013-02-281-6/+7
| | | | | | | | | | | | | | | | | | | | | | When CPU becomes idle, cpu_idleclock() calculates time to the next timer event in order to reprogram hw timer. Return that time in sbintime_t to the caller and pass it to acpi_cpu_idle(), where it can be used as one more factor (quite precise) to extimate furter sleep time and choose optimal sleep state. This is a preparatory change for further callout improvements will be committed in the next days. The commmit is not targeted for MFC.
* | Fix other architectures and ZFS.attilio2013-02-211-0/+1
|/ | | | Sponsored by: EMC / Isilon storage division
* Reduce diffs against i386.nyan2012-11-101-1/+3
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* Fix some KASSERTs.nyan2012-11-101-1/+3
| | | | They are missing changes from r208833, r227394 and r227442.
* MFi386: r211924nyan2012-11-101-1/+10
| | | | Register an interrupt vector for DTrace return probes.
* The 'testing memory' patch gets printed too many timeseadler2012-10-221-2/+0
| | | | Approved by: cperciva (implicit)
* Explain the upcoming delay by printing a message when the kerneleadler2012-10-221-0/+2
| | | | | | | | is about to begin testing memory. Reviewed by: dteske, adri Approved by: cperciva MFC after: 1 week
* Reverts r234074,234105,234564,234723,234989,235231-235232 and part ofattilio2012-10-091-5/+0
| | | | | | | | r234247. Use, instead, the static intializer introduced in r239923 for x86 and sparc64 intr_cpus, unwinding the code to the initial version. Reviewed by: marius
* MFi386: revision 237445nyan2012-09-231-4/+11
| | | | | | | | | | Commit changes missed from r237435. Properly calculate the signal trampoline addresses after the shared page is enabled. Handle FreeBSD ABIs without shared page support too. MFi386: revision 238792 Introduce curpcb magic variable.
* Partially revert r217515 so that the mem_range_softc variable is alwaysjhb2012-07-091-0/+3
| | | | | | | present on x86 kernels. This fixes the build of kernels that include 'device acpi' but do not include 'device mem'. MFC after: 1 month
* Add SMP/i386 suspend/resume support.iwasaki2012-05-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most part is merged from amd64. - i386/acpica/acpi_wakecode.S Replaced with amd64 code (from realmode to paging enabling code). - i386/acpica/acpi_wakeup.c Replaced with amd64 code (except for wakeup_pagetables stuff). - i386/include/pcb.h - i386/i386/genassym.c Added PCB new members (CR0, CR2, CR4, DS, ED, FS, SS, GDT, IDT, LDT and TR) needed for suspend/resume, not for context switch. - i386/i386/swtch.s Added suspendctx() and resumectx(). Note that savectx() was not changed and used for suspending (while amd64 code uses it). BSP and AP execute the same sequence, suspendctx(), acpi_wakecode() and resumectx() for suspend/resume (in case of UP system also). - i386/i386/apic_vector.s Added cpususpend(). - i386/i386/mp_machdep.c - i386/include/smp.h Added cpususpend_handler(). - i386/include/apicvar.h - kern/subr_smp.c - sys/smp.h Added IPI_SUSPEND and suspend_cpus(). - i386/i386/initcpu.c - i386/i386/machdep.c - i386/include/md_var.h - pc98/pc98/machdep.c Moved initializecpu() declarations to md_var.h. MFC after: 3 days
* Clean up the intr* MD KPI from the SMP dependency, removing a cause ofattilio2012-04-261-2/+0
| | | | | | | | | | | discrepancy between modules and kernel, but deal with SMP differences within the functions themselves. As an added bonus this also helps in terms of code readability. Requested by: gibbs Reviewed by: jhb, marius MFC after: 1 week
* MFi386: revisions 234074 and 234105nyan2012-04-221-0/+7
| | | | - Adding the BSP as an interrupt target directly in cpu_startup().
* - Fix to build a native i386 kernel without the SMP and atpic.nyan2012-03-161-0/+20
| | | | | | | | | - Merge r232744 changes to pc98. (Allow a kernel to be built with 'nodevice atpic'.) - Move ICU related defines from x86/isa/atpic.c to x86/isa/icu.h and use them in x86/x86/intr_machdep.c. Reviewed by: jhb
* Add support for the extended FPU states on amd64, both for nativekib2012-01-211-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 64bit and 32bit ABIs. As a side-effect, it enables AVX on capable CPUs. In particular: - Query the CPU support for XSAVE, list of the supported extensions and the required size of FPU save area. The hw.use_xsave tunable is provided for disabling XSAVE, and hw.xsave_mask may be used to select the enabled extensions. - Remove the FPU save area from PCB and dynamically allocate the (run-time sized) user save area on the top of the kernel stack, right above the PCB. Reorganize the thread0 PCB initialization to postpone it after BSP is queried for save area size. - The dumppcb, stoppcbs and susppcbs now do not carry the FPU state as well. FPU state is only useful for suspend, where it is saved in dynamically allocated suspfpusave area. - Use XSAVE and XRSTOR to save/restore FPU state, if supported and enabled. - Define new mcontext_t flag _MC_HASFPXSTATE, indicating that mcontext_t has a valid pointer to out-of-struct extended FPU state. Signal handlers are supplied with stack-allocated fpu state. The sigreturn(2) and setcontext(2) syscall honour the flag, allowing the signal handlers to inspect and manipilate extended state in the interrupted context. - The getcontext(2) never returns extended state, since there is no place in the fixed-sized mcontext_t to place variable-sized save area. And, since mcontext_t is embedded into ucontext_t, makes it impossible to fix in a reasonable way. Instead of extending getcontext(2) syscall, provide a sysarch(2) facility to query extended FPU state. - Add ptrace(2) support for getting and setting extended state; while there, implement missed PT_I386_{GET,SET}XMMREGS for 32bit binaries. - Change fpu_kern KPI to not expose struct fpu_kern_ctx layout to consumers, making it opaque. Internally, struct fpu_kern_ctx now contains a space for the extended state. Convert in-kernel consumers of fpu_kern KPI both on i386 and amd64. First version of the support for AVX was submitted by Tim Bird <tim.bird am sony com> on behalf of Sony. This version was written from scratch. Tested by: pho (previous version), Yamagi Burmeister <lists yamagi org> MFC after: 1 month
* Move the scsi_da_bios_params() prototype from pc98_machdep.h to md_var.hmarius2011-11-271-3/+0
| | | | | where the prototype for pc98_ata_disk_firmware_geom_adjust() also lives in order to avoid an #ifdef'ed include in cam(4).
* MFi386: revision 225936nyan2011-10-041-7/+34
| | | | | | | | | | Add some improvements in the idle table callbacks: - Replace instances of manual assembly instruction "hlt" call with halt() function calling. - In cpu_idle_mwait() avoid races in check to sched_runnable() using the same pattern used in cpu_idle_hlt() with the 'hlt' instruction. - Add comments explaining the logic behind the pattern used in cpu_idle_hlt() and other idle callbacks.
* In order to maximize the re-usability of kernel code in user space thiskmacy2011-09-161-1/+1
| | | | | | | | | | | | | patch modifies makesyscalls.sh to prefix all of the non-compatibility calls (e.g. not linux_, freebsd32_) with sys_ and updates the kernel entry points and all places in the code that use them. It also fixes an additional name space collision between the kernel function psignal and the libc function of the same name by renaming the kernel psignal kern_psignal(). By introducing this change now we will ease future MFCs that change syscalls. Reviewed by: rwatson Approved by: re (bz)
* In HEAD when doing no further checkes there is no reason use thebz2011-08-201-3/+2
| | | | | | | | | | temporary variable and check with if as TUNABLE_*_FETCH do not alter values unless successfully found the tunable. Reported by: jhb, bde MFC after: 3 days X-MFC with: r224516 Approved by: re (kib)
* Introduce a tunable to disable the time consuming parts of bootupbz2011-07-301-1/+12
| | | | | | | | | | | | | memtesting, which can easily save seconds to minutes of boot time. The tunable name is kept general to allow reusing the code in alternate frameworks. Requested by: many Discussed on: arch (a while a go) Obtained from: Sandvine Incorporated Reviewed by: sbruno Approved by: re (kib) MFC after: 2 weeks
* remove code for dynamic offlining/onlining of CPUs on x86avg2011-06-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | The code has definitely been broken for SCHED_ULE, which is a default scheduler. It may have been broken for SCHED_4BSD in more subtle ways, e.g. with manually configured CPU affinities and for interrupt devilery purposes. We still provide a way to disable individual CPUs or all hyperthreading "twin" CPUs before SMP startup. See the UPDATING entry for details. Interaction between building CPU topology and disabling CPUs still remains fuzzy: topology is first built using all availble CPUs and then the disabled CPUs should be "subtracted" from it. That doesn't work well if the resulting topology becomes non-uniform. This work is done in cooperation with Attilio Rao who in addition to reviewing also provided parts of code. PR: kern/145385 Discussed with: gcooper, ambrisko, mdf, sbruno Reviewed by: attilio Tested by: pho, pluknet X-MFC after: never
* Reinstate cpu_est_clockrate() support for P-state invariant TSC if APERF andjkim2011-04-121-19/+2
| | | | | | MPERF MSRs are available. It was disabled in r216443. Remove the earlier hack to subtract 0.5% from the calibrated frequency as DELAY(9) is little bit more reliable now.
* Use atomic load & store for TSC frequency. It may be overkill for amd64 butjkim2011-04-071-4/+5
| | | | | | | | | safer for i386 because it can be easily over 4 GHz now. More worse, it can be easily changed by user with 'machdep.tsc_freq' tunable (directly) or cpufreq(4) (indirectly). Note it is intentionally not used in performance critical paths to avoid performance regression (but we should, in theory). Alternatively, we may add "virtual TSC" with lower frequency if maximum frequency overflows 32 bits (and ignore possible incoherency as we do now).
* Implement atomic_load_acq_64(9) and atomic_store_rel_64(9) for i386. Thesejkim2011-04-061-0/+17
| | | | | | | | | | | functions are implemented with CMPXCHG8B instruction where it is available, i. e., all Pentium-class and later processors. Note this instruction is also used for atomic_store_rel_64() because a simple XCHG-like instruction for 64-bit memory access does not exist, unfortunately. If the processor lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are performed with interrupt temporarily disabled, assuming it does not support SMP. Although this assumption may be little naive, it is true in reality. This implementation is inspired by Linux.
* Deprecate tsc_present as the last of its real consumers finally disappeared.jkim2011-03-151-1/+1
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* Add a tunable "machdep.disable_tsc" to turn off TSC. Specifically, it turnsjkim2011-03-111-8/+15
| | | | | off boot-time CPU frequency calibration, DELAY(9) with TSC, and using TSC as a CPU ticker. Note tsc_present does not change by this tunable.
* Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq becausejkim2011-03-101-1/+1
| | | | it is almost always used with tsc_freq any way.
* MFi386: revision 218744nyan2011-02-191-1/+7
| | | | | To avoid excessive code duplication create wrapper for fill regs from stack frame.
* MFi386: revision 218329nyan2011-02-071-0/+6
| | | | Fix linking of the kernel without device npx.
* MFi386: revision 218327nyan2011-02-071-1/+17
| | | | | | | Clear the padding when returning context to the usermode, for MI ucontext_t and x86 MD parts. Kernel allocates the structures on the stack, and not clearing reserved fields and paddings causes leakage.
* MFi386: revision 217886nyan2011-02-071-3/+5
| | | | Set td_kstack_pages for thread0.
* Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.pluknet2011-01-211-5/+4
| | | | | | | Submitted by: perryh pluto.rain.com (previous version) Reviewed by: jhb Approved by: kib (mentor) Tested by: universe
* MFi386: revision 217515nyan2011-01-181-3/+0
| | | | The mem_range_softc is defined in mem.c.
* MFi386 r216012 by kib:gavin2011-01-021-1/+2
| | | | | | | | Calling fill_fpregs() for curthread is legitimate, and ELF coredump does this. Discussed with: kib MFC after: 3 days
* Do not subtract 0.5% from estimated frequency if DELAY(9) is driven by TSC.jkim2010-12-081-3/+7
| | | | Remove a confusing comment about converting to MHz as we never did.
* Remove npxgetregs(), npxsetregs(), fpugetregs() and fpusetregs()kib2010-11-261-77/+26
| | | | | | | | | | | | | | | | functions, they are unused. Remove 'user' from npxgetuserregs() etc. names. For {npx,fpu}{get,set}regs(), always use pcb->pcb_user_save for FPU context storage. This eliminates the need for ugly copying with overwrite of the newly added and reserved fields in ucontext on i386 to satisfy alignment requirements for fpusave() and fpurstor(). pc98 version was copied from i386. Suggested and reviewed by: bde Tested by: pho (i386 and amd64) MFC after: 1 week
* Adjust the order of operations in spinlock_enter() and spinlock_exit() tojhb2010-11-051-4/+10
| | | | | | | | | | | | | | | | | | work properly with single-stepping in a kernel debugger. Specifically, these routines have always disabled interrupts before increasing the nesting count and restored the prior state of interrupts after decreasing the nesting count to avoid problems with a nested interrupt not disabling interrupts when acquiring a spin lock. However, trap interrupts for single-stepping can still occur even when interrupts are disabled. Now the saved state of interrupts is not saved in the thread until after interrupts have been disabled and the nesting count has been increased. Similarly, the saved state from the thread cannot be read once the nesting count has been decreased to zero. To fix this, use temporary variables to store interrupt state and shuffle it between the thread's MD area and the appropriate registers. In cooperation with: bde MFC after: 1 month
* Move the <machine/mca.h> header to <x86/mca.h>.jhb2010-11-011-1/+1
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* Rename BUS_SPACE_IO and BUS_SPACE_MEM defines to BUS_SPACE_TAG_IO andnyan2010-10-311-8/+8
| | | | BUS_SPACE_TAG_MEM respectively to avoid conflict with nexus.c.
* MFi386: the part of revision 213226.nyan2010-10-241-44/+55
| | | | | | | Rewrite the i386 memory probe: - Move the base memory setup into a new basemem_setup() routine. MFC after: 1 week
* Remove trailing ", " from `sysctl machdep.idle_available' output.jkim2010-10-121-1/+2
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* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-59/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main goal of this is to generate timer interrupts only when there is some work to do. When CPU is busy interrupts are generating at full rate of hz + stathz to fullfill scheduler and timekeeping requirements. But when CPU is idle, only minimum set of interrupts (down to 8 interrupts per second per CPU now), needed to handle scheduled callouts is executed. This allows significantly increase idle CPU sleep time, increasing effect of static power-saving technologies. Also it should reduce host CPU load on virtualized systems, when guest system is idle. There is set of tunables, also available as writable sysctls, allowing to control wanted event timer subsystem behavior: kern.eventtimer.timer - allows to choose event timer hardware to use. On x86 there is up to 4 different kinds of timers. Depending on whether chosen timer is per-CPU, behavior of other options slightly differs. kern.eventtimer.periodic - allows to choose periodic and one-shot operation mode. In periodic mode, current timer hardware taken as the only source of time for time events. This mode is quite alike to previous kernel behavior. One-shot mode instead uses currently selected time counter hardware to schedule all needed events one by one and program timer to generate interrupt exactly in specified time. Default value depends of chosen timer capabilities, but one-shot mode is preferred, until other is forced by user or hardware. kern.eventtimer.singlemul - in periodic mode specifies how much times higher timer frequency should be, to not strictly alias hardclock() and statclock() events. Default values are 2 and 4, but could be reduced to 1 if extra interrupts are unwanted. kern.eventtimer.idletick - makes each CPU to receive every timer interrupt independently of whether they busy or not. By default this options is disabled. If chosen timer is per-CPU and runs in periodic mode, this option has no effect - all interrupts are generating. As soon as this patch modifies cpu_idle() on some platforms, I have also refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions (if supported) under high sleep/wakeup rate, as fast alternative to other methods. It allows SMP scheduler to wake up sleeping CPUs much faster without using IPI, significantly increasing performance on some highly task-switching loads. Tested by: many (on i386, amd64, sparc64 and powerc) H/W donated by: Gheorghe Ardelean Sponsored by: iXsystems, Inc.
* bus_add_child: change type of order parameter to u_intavg2010-09-101-2/+2
| | | | | | | | | | This reflects actual type used to store and compare child device orders. Change is mostly done via a Coccinelle (soon to be devel/coccinelle) semantic patch. Verified by LINT+modules kernel builds. Followup to: r212213 MFC after: 10 days
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