| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
|
|
|
| |
Tested on a Cavium CN5860-EVB-NIC4. This was broken for over a year.
|
| |
|
|
|
|
|
| |
support for what their boot loader refers to as the "RSYS4GBE", of which there
are two instances ("Data Processing Blocks") on the Radisys ATCA-7220.
|
|
|
|
| |
fixes booting on systems which are PCI targets.
|
| |
|
| |
|
| |
|
|
|
|
| |
COW based approach is not safe and should not be used in production.
|
|
|
|
|
| |
Approved by: cperciva
MFC after: 1 week
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
GIANT from VFS. This code is particulary broken and fragile and other
in-kernel implementations around, found in other operating systems,
don't really seem clean and solid enough to be imported at all.
If someone wants to reconsider in-kernel NTFS implementation for
inclusion again, a fair effort for completely fixing and cleaning it
up is expected.
In the while NTFS regular users can use FUSE interface and ntfs-3g
port to work with their NTFS partitions.
This is not targeted for MFC.
|
|
|
|
| |
wired mappings. If it does, it should just skip them.
|
|
|
|
|
|
|
|
|
|
| |
instruction loads/stores at its will.
The macro __compiler_membar() is currently supported for both gcc and
clang, but kernel compilation will fail otherwise.
Reviewed by: bde, kib
Discussed with: dim, theraven
MFC after: 2 weeks
|
|
|
|
|
|
| |
range-based invalidation function instead of performing per-page
invalidations. Don't bother invalidating mappings that don't have PTE_D
set, since they don't allow write access.
|
|
|
|
|
|
| |
the temporary mappings that are used to implement operations like
pmap_zero_page(). There is no reason for the MIPS pmap to deviate
from that practice.
|
|
|
|
|
|
|
| |
having PTE_RO set instead of PTE_D. This avoids some unnecessary failures
by pmap_extract_and_hold() that will have to be handled by a call to
vm_fault_hold(). Testing the PTE for both being non-zero and having PTE_V
set is redundant. The latter suffices.
|
| |
|
|
|
|
| |
efficiently invalidating address ranges.
|
|
|
|
|
|
| |
address ranges, and use this function in pmap_remove().
Tested by: jchandra
|
|
|
|
|
|
|
| |
Only RootHUB ports can be dual mode. Disallow OTG ports on external HUBs.
This simplifies some checks in the USB controller drivers.
MFC after: 1 week
|
|
|
|
| |
Mach that doesn't exist in FreeBSD.
|
|
|
|
|
| |
The first does proper checking of the argument types, while the latter
does not.
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
pmap_unmapdev()'s own direct efforts to destroy the page table entries are
redundant, so eliminate them.
Don't set PTE_W on the page table entry in pmap_kenter{,_attr}() on MIPS.
Setting PTE_W on MIPS is inconsistent with the implementation of this
function on other architectures. Moreover, PTE_W should not be set, unless
the pmap's wired mapping count is incremented, which pmap_kenter{,_attr}()
doesn't do.
MFC after: 10 days
|
|
|
|
|
|
|
| |
there is no need to check if Giant is acquired after it.
Reviewed by: kib
MFC after: 1 week
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Avoid re-walking the page table from the root for every PTE examined.
Tidy up some of pmap_remove()'s helper functions.
pmap_enter:
Set PV_TABLE_REF whenever the physical page being mapped is managed, not
just when it is writeable.
Only call pmap_update_page() when the old mapping was valid. If there was
no prior valid mapping, then pmap_update_page() serves no useful purpose.
However, it will interrupt every processor that has the pmap active.
pmap_enter_quick_locked:
Always set PTE_RO.
pmap_emulate_modified:
Don't set PV_TABLE_REF.
Eliminate a nonsensical comment.
|
| |
|
|
|
|
|
|
|
|
|
| |
allocating them on the stack of various bus_dmamap_load*() functions. The
S/G lists are stored in the DMA tags. This matches the implementation on
all other platforms.
Discussed with: scottl, gibbs
Tested by: stas (arm@)
|
|
|
|
|
|
| |
exist they don't cause "make tinderbox" to fail.
Reported by: jhb
|
|
|
|
|
|
|
|
|
|
| |
comment describing them. Both the function names and the comment had grown
stale. Quite some time has passed since these pmap implementations last
used the page's hold count to track the number of valid mapping within a
page table page. Also, returning TRUE from pmap_unwire_ptp() rather than
_pmap_unwire_ptp() eliminates a few instructions from callers like
pmap_enter_quick_locked() where pmap_unwire_ptp()'s return value is used
directly by a conditional statement.
|
|
|
|
| |
Move an assertion to the beginning of pmap_enter().
|
|
|
|
|
|
| |
for a managed page.
Tested by: jchandra
|
|
|
|
|
| |
(This works on my board because I wrote new caldata into this spot;
but this obviously won't work for stock DIR-825 units out there.)
|
|
|
|
|
|
| |
* add cam as a module to build - but build in scbus/da for now, as
"cam" as a module includes all cam devices. Hardly space saving.
* Don't build FFS snapshot support.
|
|
|
|
|
|
|
|
| |
This has an AR7240 SoC with an AR9285 wireless NIC on-board.
Since the kernel partition on the 4MiB flash is 960KiB, quite a bit
is disabled to try and squeeze the build into that. Even lzma'ed,
it's still quite large.
|
|
|
|
| |
* random is fine as a module
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
802.11n router.
The flash layout defaults to a 1 MiB section for the kernel so I'm trying
very hard to squeeze a minimialistic (LZMA compressde) kernel image into
that.
I've verified that it boots through to single user mode fine.
Issues:
* USB doesn't yet work as a module - I need to add something else to the
USB AR71xx build before that will work.
* There's no switch PHY support - but for now it quite happily behaves
as a useful dumb switch out of the box. Phew.
* Since a previous flash attempt trashed my radio configuration block,
I haven't yet verified whether the wireless works correctly.
I'll test that out shortly (read: once I re-calibrate the board somehow.)
Thanks to ray@ and the zrouter project for doing some of the initial
hard work in figuring out how to bring this board up.
|
| |
|
|
|
|
| |
The AR724X boards tend to come with minimal RAM/flash.
|
| |
|
|
|
|
|
|
|
|
|
| |
altera_avgen(4).
Fix white space nit that must have arisen during the merge from Perforce.
Submitted by: brooks
Sponsored by: DARPA, AFRL
|
|
|
|
|
|
|
|
|
|
| |
Terasic DE-4 board. Allow LED configuration to be set using loader
tunables, not just from userspace, and preconfigure LED 8 as a kernel
heartbeat. For now, this is a Nexus-attached, BERI-only driver, but it
could be used with other hard and soft cores on Altera FPGAs as well, in
principle.
Sponsored by: DARPA, AFRL
|
|
|
|
|
|
|
|
|
|
|
|
| |
are written out.
This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
initialised.
Tested:
* AP91 (AR7240+AR9285) - the existing board support didn't break;
* AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
used with Terasic's DE-4 and other similar FPGA boards. This display
is 800x480 and includes a capacitive touch screen, multi-touch
gesture recognition, etc. This device driver depends on a Cambridge-
provided IP core that allows the MTL device to be hooked up to the
Altera Avalon SoC bus, and also provides a VGA-like text frame buffer.
Although it is compiled as a single device driver, it actually
implements a number of different device nodes exporting various
aspects of this multi-function device to userspace:
- Simple memory-mapped driver for the MTL 24-bit pixel frame buffer.
- Simple memory-mapped driver for the MTL control register set.
- Simple memory-mapped driver for the MTL text frame buffer.
- syscons attachment for the MTL text frame buffer.
This driver attaches directly to Nexus as is common for SoC device
drivers, and for the time being is considered BERI-specific, although
in principle it might be used with other hard and soft cores on
Altera FPGAs.
Control registers, including touchscreen input, are simply memory
mapped; in the future it would be desirable to hook up a more
conventional device node that can stream events, support kqueue(2)/
poll(2)/select(2), etc.
This is the first use of syscons on MIPS, as far as I can tell, and
there are some loose ends, such as an inability to use the hardware
cursor. More fundamentally, it appears that syscons(4) assumes that
either a host is PC-like (i386, amd64) *or* it must be using a
graphical frame buffer. While the MTL supports a graphical frame
buffer, using the text frame buffer is preferable for console use.
Fixing this issue in syscons(4) requires non-trivial changes, as the
text frame buffer support assumes that direct memory access can be
done to the text frame buffer without using bus accessor methods,
which is not the case on MIPS. As a workaround for this, we instead
double-buffer and pretend to be a graphical frame buffer exposing
text accessor methods, leading to some quirks in syscons behaviour.
Sponsored by: DARPA, AFRL
|
|
|
|
|
|
|
|
|
|
|
| |
The driver attempts to support all documented parts, but has only been
tested with the 512Mbit part on the Terasic DE4 FPGA board. It should be
trivial to adapt the driver's attach routine to other embedded boards
using with any parts in the family.
Also import isfctl(8) which can be used to erase sections of the flash.
Sponsored by: DARPA, AFRL
|
|
|
|
| |
Sponsored by: DARPA, AFRL
|
|
|
|
| |
touchscreen driver yet.
|
|
|
|
|
| |
we call vm_page_dirty(). Maintaining the PV_TABLE_MOD flag, in addition,
serves no useful purpose.
|
|
|
|
|
|
| |
Terasic DE-4, and Terasic tPad Altera-based boards.
Sponsored by: DARPA, AFRL
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG. This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores. As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints. UART instances appear in /dev
as ttyu0, ttyu1, etc.
However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues. We work around
these as best we can, using various heuristics.
While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.
Sponsored by: DARPA, AFRL
|