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* The Lanner MR-730 uses the first two MACs at its MAC base for the 10/100jmallett2011-02-122-4/+37
| | | | | management ports, and gigabit ports start at an offset of 2 from the MAC base.
* Allow the platform code to return a bitmask of running cores rather than justjmallett2011-02-125-22/+30
| | | | | | | | | | | | | | a number of cores, this allows for a sparse set of CPUs. Implement support for sparse core masks on Octeon. XXX jeff@ suggests that all_cpus should include cores that are offline or running other applications/OSes, so the platform API should be further extended to allow us to set all_cpus to include all cores that are physically-present as opposed to only those that are running FreeBSD. Submitted by: Bhanu Prakash (with modifications) Reviewed by: jchandra Glanced at by: kib, jeff, jhb
* o) Cavium Octeon doesn't need nop barriers.jmallett2011-02-061-0/+42
| | | | | | | | o) Have mips_wblush just do syncw, not sync on Cavium Octeon. o) Add support for reading and writing some Octeon-specific registers. NB: Some of these are not entirely Octeon-specific. Submitted by: Bhanu Prakash
* Replace __LP64__ with __mips_n64. This partly reverts r217147.tijl2011-02-044-12/+12
| | | | | Requested by: jmallett, imp Approved by: kib (mentor)
* Put the general logic for being a CPU hog into a new functionmdf2011-02-021-2/+1
| | | | | | | | | | should_yield(). Use this in various places. Encapsulate the common case of check-and-yield into a new function maybe_yield(). Change several checks for a magic number of iterations to use should_yield() instead. MFC after: 1 week
* Implement sf_buf using direct map (XKPHYS) in MIPS n64.jchandra2011-01-273-3/+40
| | | | | | | | | | - Provide trivial implementation of sf_buf_alloc(), sf_buf_free(), sf_buf_kva() and sf_buf_page() using direct map for n64. - uio_machdep.c - use macros so that the direct map will be used in case of n64. Reviewed by: imp (earlier version) Obtained from: jmallett (user/jmallett/octeon)
* Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.pluknet2011-01-212-4/+2
| | | | | | | Submitted by: perryh pluto.rain.com (previous version) Reviewed by: jhb Approved by: kib (mentor) Tested by: universe
* If there is no WQE available for a packet that needs segmentation, drop itjmallett2011-01-201-1/+6
| | | | and return.
* Remove some compile-time options from the driver, particularly async IOBDMAjmallett2011-01-204-114/+19
| | | | | support which is unused on FreeBSD and which complicates working on the code now, can easily be added back later by someone determined to use it.
* Use simplified ldscripts rather than specific onesimp2011-01-203-3/+3
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* Move 'cpu CPU_RMI' to std.xlr, this is common for all XLR cpus.jchandra2011-01-204-14/+4
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* Re-format XLR configuartion files and remove obsolete options.jchandra2011-01-203-104/+93
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* ldscript and conf cleanup for MIPSjchandra2011-01-204-15/+7
| | | | | | | | | - Remove sys/conf/ldscript.mips.64 and sys/conf/ldscript.mips.n32 and use ldscript.mips for all ABIs. The default OUTPUT_FORMAT of the toolchain is correct. - Remove LDSCRIPT_NAME entires from XLR n32 and n64 conf files. - Remove TARGET_BIG_ENDIAN from XLR conf files. - Fix machine entry in XLRN32
* Fixes in the XLR platform codejchandra2011-01-202-3/+3
| | | | | - Fix bug in pic.h, assign reg variable, before return. - In xlr_pci.c, need to ignore the result of mmio read.
* Fix build by changing format for size_t to %jdgonzo2011-01-201-14/+14
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* Introduce signed and unsigned version of CTLTYPE_QUAD, renamingmdf2011-01-192-6/+6
| | | | existing uses. Rename sysctl_handle_quad() to sysctl_handle_64().
* Fix format of physical addresses; this fixes the n32 build.jmallett2011-01-191-3/+3
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* Don't do a device_identify to add uart0, it's already hinted.jmallett2011-01-191-8/+0
| | | | Reported by: imp
* For architectures not using direct map , and requiring real KVA page forkib2011-01-181-1/+1
| | | | | | | | | | | | | | sf buf allocation, use wakeup() instead of wakeup_one() to notify sf buffer waiters about free buffer. sf_buf_alloc() calls msleep(PCATCH) when SFB_CATCH flag was given, and for simultaneous wakeup and signal delivery, msleep() returns EINTR/ERESTART despite the thread was selected for wakeup_one(). As result, we loose a wakeup, and some other waiter will not be woken up. Reported and tested by: az Reviewed by: alc, jhb MFC after: 1 week
* Remove empty dev_mem_md_init() stubs.jkim2011-01-171-5/+0
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* Save the CPU model, the board and the CPU clock rate so they are reported byimp2011-01-171-9/+16
| | | | the approrpiate sysctl.
* Kill redundant cpu lineimp2011-01-171-1/+0
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* Make cpu_model public (otherwise there's no way to set it) and bump itimp2011-01-171-1/+4
| | | | | to 80 characters. Add hw.board to export board information, if known, from the mips kernel.
* Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().jkim2011-01-171-1/+4
| | | | | | | | | Compile sys/dev/mem/memutil.c for all supported platforms and remove now unnecessary dev_mem_md_init(). Consistently define mem_range_softc from mem.c for all platforms. Add missing #include guards for machine/memdev.h and sys/memrange.h. Clean up some nearby style(9) nits. MFC after: 1 month
* Support for 64 bit PTEs on n32 and n64 compilation.jchandra2011-01-1311-120/+159
| | | | | | | | | | | | | | | | | | | | In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version)
* Cleanup physical address and PTE types on MIPS.jchandra2011-01-135-47/+41
| | | | | | | | | | | | | | | | | | | 1. Use vm_paddr_t for physical addresses. There are a few places in the MIPS platform code where vm_offset_t is used for physical addresses, change these to use vm_paddr_t: - phys_avail[], physmem_desc[] arrays - pmap_mapdev(), page_is_managed(), is_cacheable_mem() pmap_map() args - local variables of various pmap functions 2. Change init_pte_prot() return from int to pt_entry_t, as this can be 64 bit when using 64 bit TLB entries. 3. Update printing of pt_entry_t and of vm_paddr_t to use 'j' format with uintmax_t. This will be useful later if we plan to use 64bit phsical addr on 32 bit n32 compilation. Reviewed by: imp
* The message ring interrupt needs to be enabled for all cpus, not justjchandra2011-01-121-65/+52
| | | | | | | | | | | | | the ones which run the message ring handler. Some bits of the interrupt mask are part of the status register which is saved with the process context, and these bits are initialized from the cpu on which the process is created. This means that all the processes should have the same value for these interrupt mask bits, so that the interrupt mask remains the same regardless of what thread is scheduled on the cpu. Submitted by: Sriram Gorti (srgorti at netlogicmicro dot com)
* Remove unneeded includes of <sys/linker_set.h>. Other headers that usejhb2011-01-113-3/+0
| | | | | | it internally contain nested includes. Reviewed by: bde
* Initialize PCIe buses and add preliminary support for 64-bit BARs.jmallett2011-01-111-215/+321
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* Count output bytes and packets.jmallett2011-01-102-2/+8
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* Shorten device name so it fits into vmstat -i.jmallett2011-01-101-3/+3
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* o) Free mbufs in error cases.jmallett2011-01-101-0/+6
| | | | | | o) Clear/acknowledge receive interrupt at end of thread. This gives the management interfaces performance on the order of 100Mbps rather than the previous level of 10Mbps on my MR-730.
* o) Expand the CIU driver to be aware of newly-allocated parts of the IRQ range.jmallett2011-01-105-1/+528
| | | | | | | | | | | | | | | o) Add 'octm', a trivial driver for the 10/100 management ports found on some Octeon systems. o) Make the Simple Executive's management port helper routines compile on FreeBSD (namely by not doing math on void pointers.) o) Add a cvmx_mgmt_port_sendm routine to the Simple Executive to send an mbuf so there is only one copy in the transmit path, rather than having to first copy the mbuf to an intermediate buffer and then copy that to the Simple Executive's transmit ring. o) Properly work out MII addresses of management ports on the Lanner MR-730. XXX The MR-730 also needs some patches to the MII read/write routines, but this is sufficient for now. Media detection will be fixed in the future when I can spend more time reading the vendor-supplied patches.
* Now that we correctly enable rx interrupts on all cores, performance has gottenjmallett2011-01-091-1/+22
| | | | | | | | | | | | | quite awful, because e.g. 4 packets will come in and get processed on 4 different cores at the same time, really battling with the TCP stack quite painfully. For now, just run one task at a time. This gets performance up in most cases to where it was before the correctness fixes that got interrupts to run on all cores (except in high-load TCP transmit cases where all we're handling receive for is ACKs) and in some cases it's better now. What would be ideal would be to use a more advanced interrupt mitigation strategy and possibly to use different workqueue groups per port for multi-port systems, and so on, but this is a fine stopgap.
* o) Remove some unused local definitions of IP protocol numbers.jmallett2011-01-092-11/+10
| | | | | o) Use CPU_FOREACH rather than a miscrafted for loop with an off-by-one to enable workq interrupts on all cores.
* Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.kib2011-01-091-11/+0
| | | | | | | Update the outdated comments describing MAXSLP and the process selection algorithm for swap out. Comments wording and reviewed by: alc
* Add missing ar91xx definition for the WMAC reset control.adrian2011-01-091-0/+1
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* White space changes to align comments. The mips and powerpc _inttypes.htijl2011-01-081-110/+110
| | | | | | are now exactly the same. Approved by: kib (mentor)
* Rename PRIreg helper macro to PRIptr to better reflect its use. Registerstijl2011-01-081-46/+48
| | | | | | | | | | | | and pointers don't always have the same size, e.g. the __mips_n32 ABI (ILP32) has 64 bit registers but 32 bit pointers. On mips introduce PRIptr to fix the format specifier for (u)intptr_t. Prefix PRI64 and PRIptr with underscores because macro names starting with PRI[a-zX] are reserved for future use. Approved by: kib (mentor)
* On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather thantijl2011-01-083-38/+28
| | | | | | | | | | | | | architecture macros (__mips_n64, __powerpc64__) when 64 bit types (and corresponding macros) are different from 32 bit. [1] Correct the type of INT64_MIN, INT64_MAX and UINT64_MAX. Define (U)INTMAX_C as an alias for (U)INT64_C matching the type definition for (u)intmax_t. Do this on all architectures for consistency. Suggested by: bde [1] Approved by: kib (mentor)
* On 32 bit architectures define (u)int64_t as (unsigned) long long insteadtijl2011-01-081-11/+6
| | | | | | | | | | | | | | | | of (unsigned) int __attribute__((__mode__(__DI__))). This aligns better with macros such as (U)INT64_C, (U)INT64_MAX, etc. which assume (u)int64_t has type (unsigned) long long. The mode attribute was used because long long wasn't standardised until C99. Nowadays compilers should support long long and use of the mode attribute is discouraged according to GCC Internals documentation. The type definition has to be marked with __extension__ to support compilation with "-std=c89 -pedantic". Discussed with: bde Approved by: kib (mentor)
* Fix types of some values in machine/_limits.h.tijl2011-01-081-6/+4
| | | | | | | | | | | | | | | | | On some architectures UCHAR_MAX and USHRT_MAX had type unsigned int. However, lacking integer suffixes for types smaller than int, their type should correspond to that of an object of type unsigned char (or short) when used in an expression with objects of type int. In that case unsigned char (short) are promoted to int (i.e. signed) so the type of UCHAR_MAX and USHRT_MAX should also be int. Where MIN/MAX constants implicitly have the correct type the suffix has been removed. While here, correct some comments. Reviewed by: bde Approved by: kib (mentor)
* Remove unused support for 64 bit long on 32 bit architectures.tijl2011-01-071-11/+3
| | | | | | | | It was used mainly to discover and fix some 64-bit portability problems before 64-bit arches were widely available. Discussed with: bde Approved by: kib (mentor)
* Add AT_STACKPROT elf aux vector. Will be used to inform rtld about thekib2011-01-071-1/+2
| | | | initial stack protection set by the kernel image activator.
* Remove bogus usage of INTR_FAST. "Fast" interrupts are now indicated byjhb2011-01-064-5/+5
| | | | | registering a filter handler rather than a threaded handler. Also remove a bogus use of INTR_MPSAFE for a filter.
* Correct an 8-year-old typo which reliably leads to typo after typo today:jmallett2011-01-041-42/+43
| | | | | | | | | | | | | | | | | | | The macros here for generating coprocessor 0 accessors are named like: MIPS_RDRW32_COP0 That macro would produce mips_rd_<register>() and mips_wr_<register>() inlines to access the specified register by name from C. The problem is that the R and the W were swapped in the macros originally; it was meant to be named RDWR because it generated mips_rd_* and mips_wr_* functions, but was instead spelled RDRW, which nobody should be expected to get right by anything other than copy and paste. It's too many consonants in a row to keep straight anyway, so just prefer e.g.: MIPS_RW32_COP0 While here, add a missing #undef.
* Remove OCTEON1-32. Since moving to the Cavium SDK, we've lost our support forjmallett2011-01-041-91/+0
| | | | | | | | | | | | running an o32 kernel safely, and would have to add interrupt disabling and reenabling to a bunch of macros in the Simple Executive sources to support it. The only reason one would run an o32 kernel on Octeon would be to run o32 world, which is better worked towards by adding o32 binary compatibility to n64 kernels along with, eventually, supporting multilib systems so o32 binaries can run alongside n32 and n64 ones. Discussed with: imp
* o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.jmallett2011-01-042-83/+108
| | | | | | o) Make the octeon_wdog driver work on multi-CPU systems and to also print more information on NMI that may aid debugging. Simplify and clean up internal API and structure.
* o) Unmask Central Interrupt Unit interrupts on APs, too.jmallett2011-01-041-4/+5
| | | | | | o) There's no good reason to make the low bits of the ebase the core number. While per-CPU exception bases would be nice, for now we just need to make ebase the same on all cores.
* o) When trying to determine whether the pcpu pointer is a managed address, checkjmallett2011-01-011-5/+17
| | | | | | | | | | | | not just that it is greater than the minimal kernel virtual address, but also that it is less than the maximal kernel virtual address. On n64 kernels, the pcpup comes out of a direct-mapped address that, with an unsigned compare, is rather greater than the minimal kernel virtual address. o) Turn the panic if interrupts are disabled in cpu_idle into a KASSERT since on other architectures it's behind INVARIANTS anyway. o) Add a check that not all interrupts are masked, too. o) Add cpu_idleclock() and cpu_activeclock() use to cpu_idle as is done on other architectures.
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