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* At the risk of reducing source compatibility with old NetBSD and Sprite:jmallett2012-03-0610-489/+79
| | | | | | | | | | | | | | | | | | | | | o) Get rid of some unused macros related to features we don't intend to provide. o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to support anything that predartes MIPS-III. o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being used already. o) Eliminate a duplicate and mostly-unused set of exception vector macros. There's still considerable duplication and lots more obsolete in our headers, but this reduces one of the larger files to a size where one could reckon about the correctness of its contents with a mere few hours of contemplation. There is, of course, a question of whether we need definitions for fields, registers and configurations that we are unlikely to ever use or implement, even if they're not obsolete since 1991. FreeBSD is not a processor reference manual, and things that aren't used may be wrong, or may be duplicated because nobody could possibly actually know whether they're already defined.
* Garbage collect some unused symbols.jmallett2012-03-061-8/+0
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* Make the native sigreturn just wrap set_mcontext, much as freebsd32_sigreturnjmallett2012-03-061-34/+5
| | | | does.
* Store TLS base in the sigframe just as is done in freebsd32_sendsig. Becausejmallett2012-03-061-0/+1
| | | | | | | the native sigreturn doesn't use set_mcontext like the COMPAT_FREEBSD32 version does, this wouldn't actually result in overwriting the TLS base. Probably it makes sense to restructure the native sigreturn to use set_mcontext for consistency, and to allow sigreturn to change the TLS base.
* Fix two and a half oversights in COMPAT_FREEBSD32 related to contexts andjmallett2012-03-062-3/+4
| | | | | | | | | | | | | TLS: o) The mc_tls field used to store the TLS base when doing context gets and restores was left a pointer and not converted to a 32-bit integer. This had the bug of not correctly capturing the TLS value desired by the user, and the extra nastiness of making the structure the wrong size. o) The mc_tls field was not being saved by sendsig. As a result, the TLS base would always be set to NULL when restoring from a signal handler. Thanks to gonzo for helping track down a bunch of other TLS bugs that came out of tracking these down.
* When emulating rdhwr for TLS, use the 32-bit offset under COMPAT_FREEBSD32.jmallett2012-03-062-0/+12
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* Prepare for large TLS redo. Save pointer to the beginning of TLS area,gonzo2012-03-063-20/+51
| | | | | | and offset it only if requested by RDHWR handler. Otherwise things get overly complicated - we need to track whether address passsed in request for setting td_md.md_tls is already offseted or not.
* In the trap messages that aid the primitive debugging environment of MIPS,jmallett2012-03-061-6/+14
| | | | | include the tid as well, so it's easier to tell which thread of a process with multiple is responsible for a crash.
* Fix tls base computation with COMPAT_FREEBSD32 on n64 kernels. The previousjmallett2012-03-041-5/+9
| | | | | | | | | version was missing an else and would always use the n64 TP_OFFSET. Eliminate some duplication of logic here. It may be worth getting rid of some of the ifdefs and introducing gratuitous SV_ILP32 runtime checks on n64 kernels without COMPAT_FREEBSD32 and on o32 kernels, similarly to how PowerPC works.
* Unbreak n64 build without COMPAT_FREEBSD32 by fixing mismatched preprocessorjmallett2012-03-031-1/+1
| | | | conditionals.
* o) Add COMPAT_FREEBSD32 support for MIPS kernels using the n64 ABI with ↵jmallett2012-03-0313-42/+707
| | | | | | | | | | | | | | | | | | | | | userlands using the o32 ABI. This mostly follows nwhitehorn's lead in implementing COMPAT_FREEBSD32 on powerpc64. o) Add a new type to the freebsd32 compat layer, time32_t, which is time_t in the 32-bit ABI being used. Since the MIPS port is relatively-new, even the 32-bit ABIs use a 64-bit time_t. o) Because time{spec,val}32 has the same size and layout as time{spec,val} on MIPS with 32-bit compatibility, then, disable some code which assumes otherwise wrongly when built for MIPS. A more general macro to check in this case would seem like a good idea eventually. If someone adds support for using n32 userland with n64 kernels on MIPS, then they will have to add a variety of flags related to each piece of the ABI that can vary. That's probably the right time to generalize further. o) Add MIPS to the list of architectures which use PAD64_REQUIRED in the freebsd32 compat code. Probably this should be generalized at some point. Reviewed by: gonzo
* When creating a handle for a subregion, be sure to actually math out the newjmallett2012-03-022-10/+8
| | | | | | | | handle address, where we're using handles as raw addresses. This fixes devices with subregions on Octeon PCI specifically, and likely also on MIPS more generally, where there isn't another bus_space in use that was doing the math already.
* If an Atheros device is attached to an Octeon, it's going to be by PCI.jmallett2012-03-021-0/+1
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* Unbreak SMP on stock Octeon systems -- copy the core_mask from bootinfo intojmallett2012-03-021-0/+1
| | | | sysinfo. This should have been done as part of replacing bootinfo with sysinfo.
* - Change contigmalloc() to use the vm_paddr_t type instead of an unsignedjhb2012-03-011-5/+5
| | | | | | | | | | | | | | | long for specifying a boundary constraint. - Change bus_dma tags to use bus_addr_t instead of bus_size_t for boundary constraints. These allow boundary constraints to be fully expressed for cases where sizeof(bus_addr_t) != sizeof(bus_size_t). Specifically, it allows a driver to properly specify a 4GB boundary in a PAE kernel. Note that this cannot be safely MFC'd without a lot of compat shims due to KBI changes, so I do not intend to merge it. Reviewed by: scottl
* Revert part of old logic of assigning MAC addressess:gonzo2012-02-293-16/+34
| | | | | | | | - Reserver respective number of addresses for managment port - octm uses base address directly - other drivers get MACs on "first come first served" basis Reviewed by: juli
* Correct capitalization of "Hz" in user-visible text (manpages, printf(),gavin2012-02-281-3/+3
| | | | | | etc). MFC after: 3 days
* Refctor address assignment for Octeon's ethernet ports:gonzo2012-02-229-52/+71
| | | | | | | | - Centralize address assignment - Make sure managment ports get first MAC address in pool - Properly propagate fail if address allocation failed Submitted by: Andrew Duane <aduane@juniper.net>
* When initialising the CP0 status register during boot on 64-bit MIPS,rwatson2012-02-141-1/+1
| | | | | | | | | | | | set all three of the kernel, supervisor, and user-mode 64-bit mode flags. While FreeBSD does not currently use the supervisor ring (and hence this is effectively a NOP on most systems), doing this avoids triggering an exception on 64-bit MIPS CPUs that don't support 32-bit compatibility mode, and therefore don't allow clearing the SX bit. Reviewed by: gonzo MFC after: 3 days Sponsored by: DARPA, SRI International
* - Reverse logic so base tls is fixed up with correct numbergonzo2012-02-101-1/+1
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* - Fix spelling of R_MIPS_RELGOTgonzo2012-02-101-2/+20
| | | | | | | - Add R_MIPS_JALR relocation - Add TLS relocation types Obtained from: NetBSD
* Fix-up value passed by thr_new syscall to make it compatiblegonzo2012-02-101-1/+12
| | | | with MIPS_TLS_GET/MIPS_TLS_SET sysarch API.
* Fix n32 build breakagegonzo2012-02-091-2/+2
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* - Emulate RDHWR instruction for TLS supportgonzo2012-02-092-3/+34
| | | | | | | | | | | Reading register $29 with RDHWR is becoming the de-facto standard to implement TLS. According to linux-mips wiki, MIPS Technologies has reserved hardware register $29 for ABI use. Furthermore current GCC makes the following assumptions: - RDHWR is natively available or otherwise emulated by the kernel - Register $29 holds the TLS pointer Submitted by: Robert Millan <rmh@debian.org>
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+15
| | | | Reviewed by: bde
* We use port_index field of struct octusb_qh to reference USB stategonzo2012-01-202-16/+25
| | | | | | | | | of root HUB. Although it is initialized with port index of the device's parent hub, which is worng. So track the USB tree up to root HUB and initialize this filed ptroprly Rename port_index to root_port_index in order to reflect its real semantics.
* Add parentheses where required. Without them, `sizeof LDBL_MAX'das2012-01-201-4/+4
| | | | | is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a syntax error and should be. Thanks to bde for the examples.
* Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.das2012-01-161-1/+1
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* Remove a confused comment and fix some minor bugs.das2012-01-161-7/+6
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* Stop overloading opt_global.h.adrian2012-01-162-0/+3
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* Build some more things (random, bridge/gif/gre, gpio, USB) as modules as welladrian2012-01-151-2/+3
| | | | | so some embedded platform builds can use these instead of a fully monolithic kernel.
* Some of the atheros based embedded devices use one or more PCI NICsadrian2012-01-151-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | on-board, glued to the AR71xx CPU. These may forgo separate WMAC EEPROMs (which store configuration and calibration data) and instead store it in the main board SPI flash. Normally the NIC reads the EEPROM attached to it to setup various PCI configuration registers. If this isn't done, the device will probe as something different (eg 0x168c:abcd, or 0x168c:ff??.) Other setup registers are also written to which may control important functions. This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the use of this particular code. The ART offset in the SPI flash can be specified as a hint against the relevant slot/device number, for example: hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000 hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000 TODO: * Think of a better name; * Make the PCIe version of this fixup code also use this option; * Maybe also check slot 19; * This has to happen _before_ the SPI flash is set from memory-mapped to SPI-IO - so document that somewhere.
* Fix backtrace for MIPS64:gonzo2012-01-133-15/+38
| | | | | | - Properly print 64-bit addresses - Get whole 64 bits of address using kdbpeekd - Make check for kernel address compatible with MIPS64
* - Fix .rela case of R_MIPS_26 relocation. Addednds save diferently forgonzo2012-01-131-1/+5
| | | | | .rel and .rela sections. It's shifted right two bits for former but saved as-is for latter.
* Fix relocations for MIPS64:gonzo2012-01-081-17/+82
| | | | | | | | - Use Elf32_Addr as default, the only field that is 64 bitw wide is R_MIPS_64 - Add R_MIPS_HIGHER and R_MIPS_HGHEST handlers - Handle R_MIPS_HI16 and R_MIPS_LO16 for both .rel and .rela sections
* Fix DDB x/i addr[,count] command for count > 1 casegonzo2012-01-081-0/+1
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* Fix the ar724x shift calculation when writing to the PCI config space.adrian2012-01-071-1/+1
| | | | | | | | | | | | | | | | This was preventing the ath driver from being loaded at runtime. It worked fine when compiled statically into the kernel but not when kldload'ed after the system booted. The root cause was that PCIR_INTLINE (register 60) was being overwritten by zeros when register 62 was being written to. A subsequent read of this register would return 0, and thus the rest of the PCI glue assumed an IRQ resource had already been allocated. This caused the device to fail to attach at runtime as the device itself didn't contain any IRQ resources. TODO: go back over the ar71xx and ar724x PCI config read/write code and ensure it's correct.
* - Add better COP2 (crypto coprocessor) context handler for Octeon. Keepgonzo2012-01-0617-111/+1231
| | | | | COP2 disabled and lazily allocate COP2 context structure in exception handler. Keep kernel and userland contexts separated.
* This isn't required any longer - it turns out the flashadrian2012-01-051-13/+4
| | | | | has ~ 1.7MB of space for a kernel. There's thus plenty of space for a full, non-module kernel.
* Use geom_uncompress now, rather than geom_uzip.adrian2012-01-051-4/+4
| | | | | This results in a much smaller rootfs image and it easily fits in the 8MB flash.
* Apply the same change as in r229494.andreast2012-01-041-3/+11
| | | | Requested by: ed
* - Octeon-SDK strictly requires multi_count to be zero forgonzo2012-01-031-1/+1
| | | | full and low speed devices.
* - Properly set IRQ handlers for all USB portsgonzo2012-01-012-37/+47
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* This particular work around isn't required any longer, now that theadrian2011-12-311-4/+0
| | | | | | 11n radio backends are also added into the RF linker set. This saves around 7k from the kernel binary.
* - struct clocktime sets different ranges for DOW and monthgonzo2011-12-311-10/+17
| | | | | | | comparing to struct timeval. for clocktime they should be 1..7 and 1..12 respectively - CAPK-0100ND uses RTC without centruy bit (DS1307) so set it 21st
* Oops - this was referencing a local file, which I've done away with.adrian2011-12-311-1/+1
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* - Pass proper endpoint number (without direction flag) togonzo2011-12-311-1/+1
| | | | cvmx_usb_open_pipe
* Add a configuration file for the Atheros PB47 reference board.adrian2011-12-302-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an AR71xx based board with 8MB flash, 64MB RAM, a Mini-PCI+ slot (see below) and a single 10/100/1000baseT ethernet port. It also has two USB ports. This is an easier board than most to add as it doesn't have a switch PHY on-board. This made it (mostly) trivial to craft a working configuration. Things to note: * This, like most other reference boards, use uboot rather then redboot. It means that you typically have to manually flash both the kernel and rootfs partitions. * Since there's currently no (nice) way to extract out the ethernet MAC and RAM from the uboot environment, the RAM will default to 32mb and the MAC will be something very incorrect. I'll try to fix this up in a subsequent commit or two, even if it's just some hard-coded nonsense in ar71xx_machdep.c for now. * The board is designed for a specific model of mini-PCI+ NIC which never made it into production. Normal mini-PCI NICs will work fine; if you happen to have the NIC in question then it will work fine with this board.
* Add a couple of missing wlan modules.adrian2011-12-301-1/+1
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* Remove trailing white-space.marcel2011-12-301-4/+4
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