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* Use VM_MEMATTR_UNCACHEABLE for the constant for UC memory rather thanjhb2012-03-291-1/+1
| | | | | | | VM_MEMATTR_UNCACHED. VM_MEMATTR_UNCACHEABLE is the constant other platforms use. MFC after: 2 weeks
* Remove unnecessary assembly code.jchandra2012-03-292-30/+26
| | | | | The compiler should generate lw/sw corresponding to register operations.
* Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.jmallett2012-03-2915-18/+18
| | | | | | | | | | | | | | | This makes our naming scheme more closely match other systems and the expectations of much third-party software. MIPS builds which are little-endian should require and exhibit no changes. Big-endian TARGET_ARCHes must be changed: From: To: mipseb mips mipsn32eb mipsn32 mips64eb mips64 An entry has been added to UPDATING and some foot-shooting protection (complete with warnings which should become errors in the near future) to the top-level base system Makefile.
* Turn on messages from the Simple Executive codebase, what few there are.jmallett2012-03-291-0/+3
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* Disable FP instruction emulation by default on !o32 because of ABI concerns.jmallett2012-03-291-0/+19
| | | | | Note that in practice this isn't needed because we get a coprocessor unusable exception first, but that's actually something like a bug.
* Supply endianness implied by the -m flag when compiling ucore code.jmallett2012-03-291-1/+1
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* Fix little-endian built.jmallett2012-03-291-1/+1
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* Add software PMC support.fabient2012-03-281-1/+1
| | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
* Fix size of PCI softc.jchandra2012-03-271-1/+2
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* Resource allocation for XLP SoC SDHCI slotsjchandra2012-03-272-0/+21
| | | | | | | | The on-chip SD slots do not have PCI BARs corresponding to them, so this has to be handled in the custom SoC memory allocation. Provide memory resource for rids corresponding to BAR 0 and 1 in the custom allocation code.
* Update memory and resource allocation code for SoC devicesjchandra2012-03-279-375/+343
| | | | | | | | | | | | | | | | The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
* NOR flash driver for XLP.jchandra2012-03-274-0/+93
| | | | | The NOR interface on the SoC appears on the top level PCI bus. Add a simple driver for this.
* XLP UART code udpate.jchandra2012-03-274-27/+35
| | | | | | | Move XLP PCI UART device to sys/mips/nlm/dev/ directory. Other drivers for the XLP SoC devices will be added here as well. Update uart_cpu_xlp.c and uart_pci_xlp.c use macros for uart port, speed and IO frequency.
* xlpge : driver for XLP network acceleratorjchandra2012-03-2723-7/+6861
| | | | | | | | | | | | | Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
* Support for EEPROM and CPLD on XLP EVP boards.jchandra2012-03-277-24/+487
| | | | | | | On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
* Opencrypto driver for XLP Security and RSA/ECC blocksjchandra2012-03-2710-0/+3518
| | | | | | | | Support for the Security and RSA blocks on XLP SoC. Even though the XLP supports many more algorithms, only the ones supported in OCF have been added. Submitted by: Venkatesh J. V. (venkatesh at netlogicmicro com)
* I2C support for XLP, add hints for I2C devices and update PCI resourcejchandra2012-03-273-3/+26
| | | | allocation code.
* XLP PCIe code update.jchandra2012-03-273-50/+99
| | | | | | | | | | | | - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
* Update the L1D cache flush sequence when enabling threads.jchandra2012-03-271-7/+7
| | | | Added more comments to the code.
* Switch to interrupt based message handling for XLP 8xx B0.jchandra2012-03-271-22/+22
| | | | Fixup some style issues in the file as well.
* Support for XLP4xx and XLP 8xx B0 revisionjchandra2012-03-274-54/+159
| | | | | | | - Add 4xx processor IDs, add workaround in CPU detection code. - Update frequency detection code for XLP 8xx. - Add setting device frequency code. - Update processor ID checking code.
* Fixes to the XLP startup code.jchandra2012-03-271-6/+12
| | | | | | Changes are: - Correct the order of calling init functions. - Fix up checking excluding reset area.
* Remap PMC interrupt for all coresgonzo2012-03-243-11/+12
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* Add DTrace-related part to machine-dependent code:gonzo2012-03-242-0/+75
| | | | | - DTrace trap handler - invop-related variables (unused on MIPS but still referenced from dtrace)
* Fix pmap_kextract prototype to align it with pmap.c changegonzo2012-03-231-1/+1
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* Add pseudo-device for handling PMC interrupts and link everythinggonzo2012-03-232-0/+145
| | | | PMC-related to build
* Setup fake MODINFO variables for octeon kernelgonzo2012-03-231-0/+2
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* Rework MIPS PMC code:gonzo2012-03-222-7/+51
| | | | | | | | - Replace MIPS24K-specific code with more generic framework that will make adding new CPU support easier - Add MIPS24K support for new framework - Limit backtrace depth to 1 for stability reasons and add option HWPMC_MIPS_BACKTRACE to override this limitation
* Move PMC hook invocation to cpu_intr. The idea is the same as with ast()gonzo2012-03-222-20/+12
| | | | call but there is no reason to implement it in assembler.
* Fix return type of mips pmap_kextract()jchandra2012-03-221-1/+1
| | | | The return type should be vm_paddr_t, not vm_offset_t.
* o) Don't keep drive parameters in a global, put them in the softc.jmallett2012-03-211-60/+52
| | | | | o) Don't report a bogus stripesize. o) Eliminate a nearby gratuitous "proxy" indirection.
* Remove pty(4) from our kernel configurations.ed2012-03-216-6/+0
| | | | | | | | | | | As of FreeBSD 8, this driver should not be used. Applications that use posix_openpt(2) and openpty(3) use the pts(4) that is built into the kernel unconditionally. If it turns out high profile depend on the pty(4) module anyway, I'd rather get those fixed. So please report any issues to me. The pty(4) module is still available as a kernel module of course, so a simple `kldload pty' can be used to run old-style pseudo-terminals.
* - Fix logic for detection if further processing of PMC should be performed.gonzo2012-03-181-6/+14
| | | | | pmc_intr returns one if one of the counters actually triggered the IRQ - style(9) fixed
* style(9) changes.adrian2012-03-171-9/+10
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* Begin fleshing out MII clock rate configuration changes.adrian2012-03-175-0/+74
| | | | | | | | | | | | These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined.
* Clean-up fake preload data generator:gonzo2012-03-151-24/+19
| | | | | - Use macros to push scalar values - Fix type mismatch for module size
* Fill out fake preload structure to let userland tools like pmc(3) knowgonzo2012-03-151-0/+50
| | | | about kernel module base address and actual size
* Remove a now unneeded ARGE_UNLOCK().adrian2012-03-131-3/+0
| | | | Whilst I'm here, remove a couple blank lines.
* Fix link status handling on if_arge upon system boot to allow bootp/NFS toadrian2012-03-131-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function. From the submitter: This patch fixes an issue I encountered using an NFS root with an ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails to contact a DHCP/BOOTP server via if_arge when it otherwise should be able to. This may be the same issue that Monthadar Al Jaberi reported against an RSPRO on 6 March, as the signature is the same: %%% DHCP/BOOTP timeout for server 255.255.255.255 DHCP/BOOTP timeout for server 255.255.255.255 DHCP/BOOTP timeout for server 255.255.255.255 . . . DHCP/BOOTP timeout for server 255.255.255.255 DHCP/BOOTP timeout for server 255.255.255.255 arge0: initialization failed: no memory for rx buffers DHCP/BOOTP timeout for server 255.255.255.255 arge0: initialization failed: no memory for rx buffers %%% The primary issue that I found is that the DHCP/BOOTP message that bootpc_call() is sending never makes it onto the wire, which I believe is due to the following: - Last December, a change was made to the ifioctl that bootpc_call() uses to adjust the netmask around the sosend(). - The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the old one (SIOCSIFNETMASK) did not. - if_arge maintains its own sense of link state in sc->arge_link_status. - On a single-phy interface, sc->arge_link_status is initialized to 0 in arge_init_locked(). - sc->arge_link_status remains 0 until a phy state change notification causes arge_link_task to run, notice the link is up, and set it to 1. - The inits caused by the ifioctls in bootpc_call are reinitializing the interface, but not the phy, so sc->arge_link_status goes to 0 and remains there. - arge_start_locked() always sees sc->arge_link_status == 0 and returns without queuing anything. The attached patch changes arge_init_locked() such that in the single-phy case, instead of initializing sc->arge_link_status to 0, it runs arge_link_task() to set it according to the current phy state. This change has allowed my setup to mount an NFS root successfully. Submitted by: Patrick Kelsey <kelsey@ieee.org> Reviewed by: juli
* Don't build kernel.tramp on Octeon. Probably building it should be opt-injmallett2012-03-131-0/+3
| | | | | not opt-out, but I don't know enough about which ports need it to get the defaults right.
* Correctly (I hope) deallocate the if_arge RX buffer ring on arge_stop().adrian2012-03-131-0/+43
| | | | | | | | | | | | | | | | | | I had some interesting hangs until I realised I should try flushing the DDR FIFO register and lo and behold, hangs stopped occuring. I've put in a few DDR flushes here and there in case people decide to reuse some of these functions. It's very very likely they're almost all superflous. To test: * Connect to a network with a _lot_ of broadcast traffic * Do this: # while true; do ifconfig arge0 down; ifconfig arge0 up; done This fixes the mbuf exhaustion that has been reported when the interface state flaps up/down.
* Remove TARGET_BIG_ENDIAN which should have been removed previously.jmallett2012-03-121-1/+0
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* o) Use ABI, not ISA_* options, to determine whether to compile bits if libkernjmallett2012-03-1236-48/+40
| | | | | | | required for the ABI the kernel is being built for. XXX This is implemented in a kind-of nasty way that involves including source files, but it's still an improvement. o) Retire ISA_* options since they're unused and were always wrong.
* Configuration changes/updates!adrian2012-03-121-4/+12
| | | | | | | * enable ALQ and net80211/ath ALQ logging by default, to make it possible to get debug register traces. * Update some comments * Enable HWPMC for testing.
* Use 64-bit bus space constants on 64-bit kernels.jmallett2012-03-121-3/+11
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* Remove more unused stuff, primarily a set of (unused, thankfully) PIOjmallett2012-03-123-265/+3
| | | | | | functions. Adjust nearby style of one assembly function END().
* Remove more unused code and declarations, and add dire warnings to the 64-bitjmallett2012-03-129-241/+9
| | | | atomic ops used by 32-bit kernels.
* Remove platform APIs which are not used by any code and which had only stubjmallett2012-03-1213-254/+3
| | | | | | | | | implementations or no implementation on all platforms. Some of these functions might be good ideas, but their semantics were unclear given the lack of implementation, and an unlucky porter could be fooled into trying to implement them or, worse, being baffled when something like platform_trap_enter() failed to be called.
* - Rename apb_intr to apb_filter since it's a filter handlergonzo2012-03-121-5/+38
| | | | | | | - Pass interrupt trapframe for handlers dow the chain - Add PMC interrupt handler PMC interrupt is a special case, so we want handle it as soon as possible with minimum overhead. So we handle it apb filter routine.
* Begin modifying the PB92 config file to actually generate a flashable,adrian2012-03-121-28/+40
| | | | | | | | | | | | | | bootable image. The kernel has to fit inside an 896KiB area in a 4MB SPI flash. So a bunch of stuff can't be included (and more is to come), including (unfortunately) IPv6. TODO: * GPIO modules need to be created * Shrink the image a bit more by removing some of the CAM layer debugging strings.
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