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* When initialising the CP0 status register during boot on 64-bit MIPS,rwatson2012-02-141-1/+1
| | | | | | | | | | | | set all three of the kernel, supervisor, and user-mode 64-bit mode flags. While FreeBSD does not currently use the supervisor ring (and hence this is effectively a NOP on most systems), doing this avoids triggering an exception on 64-bit MIPS CPUs that don't support 32-bit compatibility mode, and therefore don't allow clearing the SX bit. Reviewed by: gonzo MFC after: 3 days Sponsored by: DARPA, SRI International
* - Reverse logic so base tls is fixed up with correct numbergonzo2012-02-101-1/+1
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* - Fix spelling of R_MIPS_RELGOTgonzo2012-02-101-2/+20
| | | | | | | - Add R_MIPS_JALR relocation - Add TLS relocation types Obtained from: NetBSD
* Fix-up value passed by thr_new syscall to make it compatiblegonzo2012-02-101-1/+12
| | | | with MIPS_TLS_GET/MIPS_TLS_SET sysarch API.
* Fix n32 build breakagegonzo2012-02-091-2/+2
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* - Emulate RDHWR instruction for TLS supportgonzo2012-02-092-3/+34
| | | | | | | | | | | Reading register $29 with RDHWR is becoming the de-facto standard to implement TLS. According to linux-mips wiki, MIPS Technologies has reserved hardware register $29 for ABI use. Furthermore current GCC makes the following assumptions: - RDHWR is natively available or otherwise emulated by the kernel - Register $29 holds the TLS pointer Submitted by: Robert Millan <rmh@debian.org>
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+15
| | | | Reviewed by: bde
* We use port_index field of struct octusb_qh to reference USB stategonzo2012-01-202-16/+25
| | | | | | | | | of root HUB. Although it is initialized with port index of the device's parent hub, which is worng. So track the USB tree up to root HUB and initialize this filed ptroprly Rename port_index to root_port_index in order to reflect its real semantics.
* Add parentheses where required. Without them, `sizeof LDBL_MAX'das2012-01-201-4/+4
| | | | | is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a syntax error and should be. Thanks to bde for the examples.
* Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.das2012-01-161-1/+1
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* Remove a confused comment and fix some minor bugs.das2012-01-161-7/+6
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* Stop overloading opt_global.h.adrian2012-01-162-0/+3
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* Build some more things (random, bridge/gif/gre, gpio, USB) as modules as welladrian2012-01-151-2/+3
| | | | | so some embedded platform builds can use these instead of a fully monolithic kernel.
* Some of the atheros based embedded devices use one or more PCI NICsadrian2012-01-151-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | on-board, glued to the AR71xx CPU. These may forgo separate WMAC EEPROMs (which store configuration and calibration data) and instead store it in the main board SPI flash. Normally the NIC reads the EEPROM attached to it to setup various PCI configuration registers. If this isn't done, the device will probe as something different (eg 0x168c:abcd, or 0x168c:ff??.) Other setup registers are also written to which may control important functions. This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the use of this particular code. The ART offset in the SPI flash can be specified as a hint against the relevant slot/device number, for example: hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000 hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000 TODO: * Think of a better name; * Make the PCIe version of this fixup code also use this option; * Maybe also check slot 19; * This has to happen _before_ the SPI flash is set from memory-mapped to SPI-IO - so document that somewhere.
* Fix backtrace for MIPS64:gonzo2012-01-133-15/+38
| | | | | | - Properly print 64-bit addresses - Get whole 64 bits of address using kdbpeekd - Make check for kernel address compatible with MIPS64
* - Fix .rela case of R_MIPS_26 relocation. Addednds save diferently forgonzo2012-01-131-1/+5
| | | | | .rel and .rela sections. It's shifted right two bits for former but saved as-is for latter.
* Fix relocations for MIPS64:gonzo2012-01-081-17/+82
| | | | | | | | - Use Elf32_Addr as default, the only field that is 64 bitw wide is R_MIPS_64 - Add R_MIPS_HIGHER and R_MIPS_HGHEST handlers - Handle R_MIPS_HI16 and R_MIPS_LO16 for both .rel and .rela sections
* Fix DDB x/i addr[,count] command for count > 1 casegonzo2012-01-081-0/+1
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* Fix the ar724x shift calculation when writing to the PCI config space.adrian2012-01-071-1/+1
| | | | | | | | | | | | | | | | This was preventing the ath driver from being loaded at runtime. It worked fine when compiled statically into the kernel but not when kldload'ed after the system booted. The root cause was that PCIR_INTLINE (register 60) was being overwritten by zeros when register 62 was being written to. A subsequent read of this register would return 0, and thus the rest of the PCI glue assumed an IRQ resource had already been allocated. This caused the device to fail to attach at runtime as the device itself didn't contain any IRQ resources. TODO: go back over the ar71xx and ar724x PCI config read/write code and ensure it's correct.
* - Add better COP2 (crypto coprocessor) context handler for Octeon. Keepgonzo2012-01-0617-111/+1231
| | | | | COP2 disabled and lazily allocate COP2 context structure in exception handler. Keep kernel and userland contexts separated.
* This isn't required any longer - it turns out the flashadrian2012-01-051-13/+4
| | | | | has ~ 1.7MB of space for a kernel. There's thus plenty of space for a full, non-module kernel.
* Use geom_uncompress now, rather than geom_uzip.adrian2012-01-051-4/+4
| | | | | This results in a much smaller rootfs image and it easily fits in the 8MB flash.
* Apply the same change as in r229494.andreast2012-01-041-3/+11
| | | | Requested by: ed
* - Octeon-SDK strictly requires multi_count to be zero forgonzo2012-01-031-1/+1
| | | | full and low speed devices.
* - Properly set IRQ handlers for all USB portsgonzo2012-01-012-37/+47
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* This particular work around isn't required any longer, now that theadrian2011-12-311-4/+0
| | | | | | 11n radio backends are also added into the RF linker set. This saves around 7k from the kernel binary.
* - struct clocktime sets different ranges for DOW and monthgonzo2011-12-311-10/+17
| | | | | | | comparing to struct timeval. for clocktime they should be 1..7 and 1..12 respectively - CAPK-0100ND uses RTC without centruy bit (DS1307) so set it 21st
* Oops - this was referencing a local file, which I've done away with.adrian2011-12-311-1/+1
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* - Pass proper endpoint number (without direction flag) togonzo2011-12-311-1/+1
| | | | cvmx_usb_open_pipe
* Add a configuration file for the Atheros PB47 reference board.adrian2011-12-302-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an AR71xx based board with 8MB flash, 64MB RAM, a Mini-PCI+ slot (see below) and a single 10/100/1000baseT ethernet port. It also has two USB ports. This is an easier board than most to add as it doesn't have a switch PHY on-board. This made it (mostly) trivial to craft a working configuration. Things to note: * This, like most other reference boards, use uboot rather then redboot. It means that you typically have to manually flash both the kernel and rootfs partitions. * Since there's currently no (nice) way to extract out the ethernet MAC and RAM from the uboot environment, the RAM will default to 32mb and the MAC will be something very incorrect. I'll try to fix this up in a subsequent commit or two, even if it's just some hard-coded nonsense in ar71xx_machdep.c for now. * The board is designed for a specific model of mini-PCI+ NIC which never made it into production. Normal mini-PCI NICs will work fine; if you happen to have the NIC in question then it will work fine with this board.
* Add a couple of missing wlan modules.adrian2011-12-301-1/+1
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* Remove trailing white-space.marcel2011-12-301-4/+4
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* Use curthread rather than PCPU_GET(curthread). 'curthread' usesjhb2011-12-291-2/+2
| | | | | | | special-case optimizations on several platforms and is preferred. Reported by: dim (indirectly) MFC after: 2 weeks
* Flesh out the RSPRO GPIO config, including the RF LED.adrian2011-12-292-0/+22
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* Break out the AR71XX config file into _BASE and board specificadrian2011-12-2910-123/+291
| | | | | | | | | | | | | | | | | | bits. The ROUERSTATION and RSPRO variants contain: * the board specific bits (eg the RTC for RSPRO, later on it'll include the GPIO/LED definitions); * the boot specific bits (eg, on-board flash, usb flash, etc). For now the AR71XX_BASE file contains the common board config, drivers and net80211/ath wireless drivers. I'll follow this up with config files for the other boards I have (eg the Ubiquiti LSSR71, as well as some Mikrotik boards that use the AR71XX and atheros reference boards) which will be quite easy to do now.
* - Add generic GPIO driver for Cavium Octeon. At the moment pin definition isgonzo2011-12-283-0/+551
| | | | hardcoded but will be changed later with more flexible way to define them.
* - Initialize compact_flash_attribute_base_addr from bootinfo structuregonzo2011-12-241-0/+2
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* - Set CF physical address base in sysinfo structuregonzo2011-12-231-0/+2
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* Remove these locks - they aren't strictly needed and cause measurableadrian2011-12-201-13/+0
| | | | | | | | | | | | | | | | | | | | performance issues. * Access to the GPIO bus is already locked by requesting and releasing the bus - thus the lock isn't really needed for each GPIO pin change. * Don't lock and unlock the GPIO bus for -each- i2c access - the i2c bus code is already doing this by calling the upper layer callback to request/release the bus. This thus locks the bus for the entirety of the transaction. TODO: * Further verify that everything is correctly requesting/ releasing the GPIO bus. * Look at how to lock the GPIO pin configuration stuff, potentially by locking/unlocking the bus at the gpiobus layer.
* Unbreak the OCTEON1 kernel build after r228483 removing the left overbz2011-12-171-1/+0
| | | | | | declaration. MFC after: 11 days
* kern cons: introduce infrastructure for console grabbing by kernelavg2011-12-171-0/+14
| | | | | | | | | | | | At the moment grab and ungrab methods of all console drivers are no-ops. Current intended meaning of the calls is that the kernel takes control of console input. In the future the semantics may be extended to mean that the calling thread takes full ownership of the console (e.g. console output from other threads could be suspended). Inspired by: bde MFC after: 2 months
* * Add in the gpio/gpioled drivers into AR91XX_BASE.adrian2011-12-153-0/+49
| | | | | | | | | * Add in a default GPIO section for AR91XX_BASE.hints, which doesn't define the GPIO function masks or any GPIO pines. * Add in the GPIO line definitions for LEDs and GPIO pins for the TP-WR1043nd. I've verified the LEDs work fine using gpioset.
* Re-jiggle the GPIO code a little to remove the hard-coded AR71xx GPIOadrian2011-12-151-25/+38
| | | | | | | | | | | | | | | | config and function mask setup. * "gpiomask" now specifies which GPIO pins to enable, for devices to bind to. * "function_set" allows bits in the function register to be set at GPIO setup. * "function_clear" allows bits in the function register to be cleared at GPIO setup. The function_set/function_clear bits allow for individual GPIO pins to either drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected, or disabling JTAG for the AR7240 (which is apparently needed ..) I've verified this on the AR71xx.
* Implement better support for USB controller suspend and resume.hselasky2011-12-147-146/+56
| | | | | | | | | | This patch should remove the need for kldunload of USB controller drivers at suspend and kldload of USB controller drivers at resume. This patch also fixes some build issues in avr32dci.c MFC after: 2 weeks
* Replace __signed by signed.ed2011-12-131-1/+1
| | | | | The signed keyword is an integral part of the C syntax. There's no need to use __signed.
* Style(9) changes.adrian2011-12-133-126/+133
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* Disable KDB/DDB options for XLP N32 compile.jchandra2011-12-051-0/+6
| | | | | | | n32 abi is not supported in KDB/DDB yet, disable the option in XLPN32 conf. Reported by: gonzo, bz
* Fix N32 compilation again for XLP.jchandra2011-12-051-1/+1
| | | | | | | Disable DDB/KDB related options for N32, and add back a cast that was lost during the last set of updates. Reported by: gonzo, bz
* Fix XLP compilation.jchandra2011-12-051-0/+2
| | | | | | | Add definitions of LSU_DEBUG_ADDR and LSU_DEBUG_DATA0, the code that uses it was added in r227799 Reported by: gonzo
* - Fix backtrace for MIPS64 platformgonzo2011-11-281-2/+5
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