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* MFC r257334, r257336, r257337, r257338, r257341, r257342, r257343, r257370,ian2014-05-141-1/+1
| | | | | | | r257368, r257416 Hints-only devices should return BUS_PROBE_NOWILDCARD from their probe methods.
* Replace kernel virtual address space allocation with vmem. This providesjeff2013-08-071-1/+1
| | | | | | | | | | | | | transparent layering and better fragmentation. - Normalize functions that allocate memory to use kmem_* - Those that allocate address space are named kva_* - Those that operate on maps are named kmap_* - Implement recursive allocation handling for kmem_arena in vmem. Reviewed by: alc Tested by: pho Sponsored by: EMC / Isilon Storage Division
* Merge from vmobj-rwlock branch:attilio2013-02-261-1/+0
| | | | | | | | Remove unused inclusion of vm/vm_pager.h and vm/vnode_pager.h. Sponsored by: EMC / Isilon storage division Tested by: pho Reviewed by: alc
* Remove platform APIs which are not used by any code and which had only stubjmallett2012-03-121-25/+0
| | | | | | | | | implementations or no implementation on all platforms. Some of these functions might be good ideas, but their semantics were unclear given the lack of implementation, and an unlucky porter could be fooled into trying to implement them or, worse, being baffled when something like platform_trap_enter() failed to be called.
* At the risk of reducing source compatibility with old NetBSD and Sprite:jmallett2012-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | | o) Get rid of some unused macros related to features we don't intend to provide. o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to support anything that predartes MIPS-III. o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being used already. o) Eliminate a duplicate and mostly-unused set of exception vector macros. There's still considerable duplication and lots more obsolete in our headers, but this reduces one of the larger files to a size where one could reckon about the correctness of its contents with a mere few hours of contemplation. There is, of course, a question of whether we need definitions for fields, registers and configurations that we are unlikely to ever use or implement, even if they're not obsolete since 1991. FreeBSD is not a processor reference manual, and things that aren't used may be wrong, or may be duplicated because nobody could possibly actually know whether they're already defined.
* Remove duplicate header includeskevlo2011-06-261-2/+0
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* Fix a brain-o in platform_cpu_mask() by just specifying a possibleattilio2011-05-131-6/+4
| | | | | | | cpuset_t to be copied, rather than return the array. I can't rely anymore on this being a simple int/long object. Reported by: art
* Add the cpuset_t conversion for mips.attilio2011-05-131-3/+10
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* Fix typos - remove duplicate "the".brucec2011-02-211-1/+1
| | | | | | PR: bin/154928 Submitted by: Eitan Adler <lists at eitanadler.com> MFC after: 3 days
* Allow the platform code to return a bitmask of running cores rather than justjmallett2011-02-121-3/+3
| | | | | | | | | | | | | | a number of cores, this allows for a sparse set of CPUs. Implement support for sparse core masks on Octeon. XXX jeff@ suggests that all_cpus should include cores that are offline or running other applications/OSes, so the platform API should be further extended to allow us to set all_cpus to include all cores that are physically-present as opposed to only those that are running FreeBSD. Submitted by: Bhanu Prakash (with modifications) Reviewed by: jchandra Glanced at by: kib, jeff, jhb
* - dump_avail layout should be sequence of [start, end)gonzo2010-12-091-3/+1
| | | | | | pairs, not <start, size>. Spotted by: alc@
* - Populate dump_avail with proper values from phys_availgonzo2010-12-091-1/+6
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* Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mipsimp2010-11-131-0/+3
| | | | | | mipsel' or 'machine mips mipseb' into the config file (with a few 64's tossed in for good measure). This will let us build the proper kernels with different worlds as part of make universe.
* Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.neel2010-09-221-1/+1
| | | | | | | Mappings with other cacheability attributes can be established, if needed, by using 'pmap_kenter_attr()'. Suggested by: jchandra, imp
* Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistentneel2010-09-151-1/+1
| | | | | | with the meaning of IM bits in the status register. Reviewed by: jmallett, jchandra
* bus_add_child: change type of order parameter to u_intavg2010-09-101-1/+1
| | | | | | | | | | This reflects actual type used to store and compare child device orders. Change is mostly done via a Coccinelle (soon to be devel/coccinelle) semantic patch. Verified by LINT+modules kernel builds. Followup to: r212213 MFC after: 10 days
* Remove redundant declaration of 'pcib_driver' class from sb_zbpci.c. Thisneel2010-08-061-1/+0
| | | | | | causes a compilation error. The declaration is provided by sys/dev/pci/pcib_private.h starting from r210864.
* Use a signed integer to hold the address of a register.neel2010-08-061-10/+10
| | | | | This does the right thing by sign extending the address when compiling for the n64 abi.
* uint64_t is 'unsigned long' in n64 build, so compiler is unhappy if theneel2010-08-061-3/+3
| | | | | | format specifier in printf is "%llu". Use "%ju" instead.
* Fix a race between clock_intr() and tick_ticker() when updatingneel2010-08-051-2/+0
| | | | | | | | | | | | | | | | | | | 'counter_upper' and 'counter_lower_last'. The race exists because interrupts are enabled even though tick_ticker() executes in a critical section. Fix a bug in clock_intr() in how it updates the cached values of 'counter_upper' and 'counter_lower_last'. They are updated only when the COUNT register rolls over. More interestingly it will *never* update the cached values if 'counter_lower_last' happens to be zero. Get rid of superfluous critical section in clock_intr(). There is no reason to do this because clock_intr() executes in hard interrupt context. Switch back to using 'tick_ticker()' as the cpu ticker for Sibyte. Reviewed by: jmallett, mav
* Remove redunant machine/cpuregs.h include.imp2010-07-131-4/+3
| | | | Also, spell things like in machine/cpuregs.h instead of machine/cpu.h.
* Fix Sibyte SMP kernel breakage caused by r208249.neel2010-05-181-0/+2
| | | | | We need to include the header file that provides declaration of the smp_topo_none() function.
* Adds JC's cleanup patches that fix it sorrs2010-05-181-0/+14
| | | | | | | | we call an platform dependant topo function as well as clean up all the XLR specific ifdefs around smp platform init. Obtained from: JC
* o) Remove default MAXMEM on SWARM; pmap can readily use lmem for >512Mjmallett2010-04-231-0/+11
| | | | | | | | physical addresses. o) Set a local maxmem in sb_machdep.c to avoid trying to use pages over 2^64 under 32-bit ABIs. Our pmap needs corrected to use vm_paddr_t consistently, then we can make vm_paddr_t 64-bit under 32-bit ABIs and add code in pmap to limit phys_avail by the maximum PFN that a 32-bit PTE can hold.
* Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.neel2010-03-262-52/+9
| | | | | | Obtained from NetBSD. Suggested by: jmallett@
* Sibyte provides a 64-bit read-only counter that counts at half the processorneel2010-03-203-0/+40
| | | | | | | | | frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync.
* Make sure that the registers 'v0' and 'v1' are properly sign-extendedneel2010-03-201-4/+4
| | | | | | | when sb_load64() returns. Some 32-bit arithmetic operations (e.g. subu) have unpredicatable results when operating on 64-bit registers that are not properly sign-extended.
* Add support for CPUs with cache coherent DMA. The two main changes are:neel2010-03-041-0/+7
| | | | | | | | | | | | - We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT requests on these CPUs. - The bus_dmamap_sync() is a no-op for these CPUs. A side-effect of this change is rename DMAMAP_COHERENT flag to DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately. Reviewed by: gonzo, imp
* Various fixes to get the SWARM config working on a big-endian Sibyte CPU.neel2010-02-173-8/+197
| | | | | | | | | | | | | Getting the little-endian PCI bus working on the big-endian CPU proved to be quite challenging. We let the PCI devices be mapped in the "match byte lanes" address window. This is where they are mapped by the CFE and DMA transfers generated to or from addresses within this window are not subject to automatic byte-swapping. However any access by the driver to memory-mapped pci space is redirected via the "match bit lanes" address window. We get the benefit of automatic byte swapping through this address window and drivers don't need to change to deal with CPU big-endianness.
* Remove the PCI_IOSPACE_SIZE and PCI_IOSPACE_ADDR hack from nexus.c. Implementneel2010-02-121-6/+126
| | | | | | | | | this in the Sibyte PCI hostbridge driver instead. The nexus driver sees resource allocation requests for memory and irq resources only. These are legitimate resources on all MIPS platforms. Suggested by: imp
* SMP support for the mips port.neel2010-02-095-7/+212
| | | | | | | The platform that supports SMP currently is a SWARM with a dual-core Sibyte processor. The kernel config file to use is SWARM_SMP. Reviewed by: imp, rrs
* Initialize interrupt controller early on.neel2010-02-051-0/+18
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* Reimplement all functions to access the system control unit in C.neel2010-02-054-126/+145
| | | | | | | | | The only reason we need to have the sb_load64() and sb_store64() functions in assembly is to cheat the compiler and generate the 'ld' and 'sd' instructions which it otherwise will not do when compiling for a 32-bit architecture. There are some 64-bit registers in the SCD unit that must be accessed using 64-bit load and store instructions.
* style: don't need to use braces for single line control statements.neel2010-02-051-10/+5
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* Install the XTLB exception handler for Sibyte processors.neel2010-01-261-0/+24
| | | | | | | | | | | | This is a workaround for the fact that the CFE is compiled as a 64-bit application and therefore sets the SR_KX bit every time we call into it (for e.g. console). A TLB miss for any address above 0xc0000000 with the SR_KX bit set will end up at the XTLB exception vector. We workaround this by copying the standard TLB handler at the XTLB exception vector. Approved by: imp (mentor)
* - Call post-boot fixup function in order to get proper staticgonzo2010-01-251-4/+2
| | | | | | | symbols resolving in DDB - When zeroing .bss/.sbss do not round end address to page boundary, it's not neccessary and might destroy data pased by trampoline or boot loader
* Remove Sibyte specific code from locore.S that sets the k0seg coherency.neel2010-01-231-0/+17
| | | | | | Move it to platform_start() instead. Approved by: imp (mentor)
* Remove redundant interrupt mapper code. We don't need to disable theimp2010-01-111-113/+8
| | | | | | | | interrupt sources feeding into a hardintr anymore. The mips_mask_hard_irq() function does that for us while an interrupt is being processed. Submitted by: neel@
* Get sb_zbpci.c compiling again after the macros PCI_BUSMAX,imp2010-01-111-0/+1
| | | | | | PCI_SLOTMAX and PCI_FUNCMAX were moved to pcireg.h. Submitted by: neel@
* Rename mips_pcpu_init to mips_pcpu0_init since it applies only to theimp2010-01-091-1/+1
| | | | BSP. Provide a missing prototype.
* Centralize initialization of pcpu, and set curthread early...imp2010-01-081-0/+3
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* Remove all CFE-specific code from locore.S. The CFE entrypoint initializationneel2010-01-061-13/+9
| | | | | | is now done in platform-specific code. Approved by: imp (mentor)
* With this commit our friend RMI will now compile. I haverrs2009-10-302-0/+7
| | | | | | not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-)
* Does 4 things:rrs2009-10-151-1/+1
| | | | | | | | | | | 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling.
* Add sibyte device support.imp2009-07-048-0/+1575
Submitted by: Neelkanth Natu
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