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* Whitespace fixes for files in sys/mips/nlmjchandra2015-02-2815-70/+68
| | | | | Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
* Fix up interrupt definitions for Broadcom XLPjchandra2015-02-261-5/+0
| | | | | | Gather all the IRQ definitions to interrupt.h. Earlier these were in xlp.h and pic.h. Update the definition of XLP_IRQ_IS_PICINTR to check for last irq as well.
* Netlogic XLP network driver updatejchandra2013-09-073-2/+17
| | | | | | | | | | Changes are to - update board and network interface detection logic - fix reading onboard CPLD in little-endian config - print NAE frequency conrrectly for Bx chips - update XAUI config to disable Rx/Tx until interface is up Submitted by: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
* Little-endian and other fixes for Broadcom XLP network driverjchandra2013-01-241-1/+1
| | | | | | | | | | | | | | | The changes are: - the microcore code loaded into the NAE has to be byteswapped in LE - the descriptors in memory for a P2P NAE descriptor has to be byteswapped in LE - the m_data pointer is already cacheline aligned, so the unnecessary m_adj to cacheline size can be removed - fix mask used to obtain physical address from the Tx freeback descriptor - fix a compile error in code under #ifdef Obtained from: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
* Fix credit configuration on Broadcom XLP CMSjchandra2013-01-241-2/+2
| | | | | | The CMS output queue credit configuration register is 64 bit, so use a 64 bit variable while updating it. Obtained from: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
* Broadcom XLP network driver update for XLP 8xx B1 revjchandra2013-01-241-0/+1
| | | | | | | | Update MDIO reset code to support Broadcom XLP B1 revisions. Update nlm_xlpge_ioctl, nlm_xlpge_port_enable need not be called after nlm_xlpge_init. Obtained from: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
* Broadcom XLP updates for the new firmwarejchandra2013-01-241-0/+13
| | | | | | | Support few more versions of board firmware. In case the security block is disabled, enable it at boot. Also increase the excluded memory region to cover the area used by the firmware to initialize devices.
* Support Netlogic XLP 8xx B1 revisions in xlpge.jchandra2012-07-091-0/+1
| | | | | Updates to the MDIO access code for the new revision of the XLP chip.
* Update memory and resource allocation code for SoC devicesjchandra2012-03-273-117/+15
| | | | | | | | | | | | | | | | The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
* xlpge : driver for XLP network acceleratorjchandra2012-03-278-1/+1724
| | | | | | | | | | | | | Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
* Support for EEPROM and CPLD on XLP EVP boards.jchandra2012-03-271-0/+100
| | | | | | | On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
* Opencrypto driver for XLP Security and RSA/ECC blocksjchandra2012-03-272-0/+608
| | | | | | | | Support for the Security and RSA blocks on XLP SoC. Even though the XLP supports many more algorithms, only the ones supported in OCF have been added. Submitted by: Venkatesh J. V. (venkatesh at netlogicmicro com)
* XLP PCIe code update.jchandra2012-03-272-8/+28
| | | | | | | | | | | | - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
* Support for XLP4xx and XLP 8xx B0 revisionjchandra2012-03-272-36/+104
| | | | | | | - Add 4xx processor IDs, add workaround in CPU detection code. - Update frequency detection code for XLP 8xx. - Add setting device frequency code. - Update processor ID checking code.
* Fix XLP compilation.jchandra2011-12-051-0/+2
| | | | | | | Add definitions of LSU_DEBUG_ADDR and LSU_DEBUG_DATA0, the code that uses it was added in r227799 Reported by: gonzo
* Merge XLP 3XX updates and related rework.jchandra2011-11-217-788/+508
| | | | | | | | | | | | | * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
* Whitespace fixes in XLP HAL files.jchandra2011-11-199-358/+358
| | | | Also fixup a macro in iomap.h
* MIPS XLP platform code update.jchandra2011-09-0516-2069/+2013
| | | | | | | | | | | | | | * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
* Add MIPS platform files for Netlogic XLP SoC.jchandra2011-07-1613-0/+3645
Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
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