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* MFR r261294:brooks2014-03-031-1/+1
| | | | | | Remove an unneeded space in the BERI merge. Sponsored by: DARPA, AFRL
* Fix other architectures and ZFS.attilio2013-02-211-0/+1
| | | | Sponsored by: EMC / Isilon storage division
* Add preliminary support for the SRI International / University of Cambridgerwatson2012-08-251-1/+6
| | | | | | | | Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs, and is being used for CPU and OS research at several institutions. Sponsored by: DARPA, AFRL
* Reinstate the XTLB handler for CPU_NLM and CPU_RMIjchandra2012-04-021-1/+1
| | | | | These platforms set the KX bit even when booted in 32 bit mode. So the XLTB handler is needed even when __mips_n64 is not defined.
* Clean-up fake preload data generator:gonzo2012-03-151-24/+19
| | | | | - Use macros to push scalar values - Fix type mismatch for module size
* Fill out fake preload structure to let userland tools like pmc(3) knowgonzo2012-03-151-0/+50
| | | | about kernel module base address and actual size
* o) Use ABI, not ISA_* options, to determine whether to compile bits if libkernjmallett2012-03-121-1/+0
| | | | | | | required for the ABI the kernel is being built for. XXX This is implemented in a kind-of nasty way that involves including source files, but it's still an improvement. o) Retire ISA_* options since they're unused and were always wrong.
* Remove more unused code and declarations, and add dire warnings to the 64-bitjmallett2012-03-121-11/+0
| | | | atomic ops used by 32-bit kernels.
* o) Remove some CPU_CNMIPS-related magical thinking about the status register'sjmallett2012-03-101-2/+1
| | | | | contents for user programs. o) Conditionalize the installation of an XTLB handler on ABI, not CPU family.
* At the risk of reducing source compatibility with old NetBSD and Sprite:jmallett2012-03-061-4/+4
| | | | | | | | | | | | | | | | | | | | | o) Get rid of some unused macros related to features we don't intend to provide. o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to support anything that predartes MIPS-III. o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being used already. o) Eliminate a duplicate and mostly-unused set of exception vector macros. There's still considerable duplication and lots more obsolete in our headers, but this reduces one of the larger files to a size where one could reckon about the correctness of its contents with a mere few hours of contemplation. There is, of course, a question of whether we need definitions for fields, registers and configurations that we are unlikely to ever use or implement, even if they're not obsolete since 1991. FreeBSD is not a processor reference manual, and things that aren't used may be wrong, or may be duplicated because nobody could possibly actually know whether they're already defined.
* Fix wakeup latency when sleeping with 'wait'jchandra2011-10-181-17/+10
| | | | | | | | | | | | | | | | | If we handle an interrupt just before the 'wait' and the interrupt schedules some work, we need to skip the 'wait' call. The simple solution of calling sched_runnable() with interrupts disabled immediately before wait still leaves a window after the call and before 'wait' in which the same issue can occur. The solution implemented is to check the EPC in the interrupt handler, and if it is in a region before the 'wait' call, to fix up the EPC to skip the wait call. Reported/analysed by: adrian Fix suggested by: kib Reviewed by: jmallett, imp
* Disable using wait in cpu_idle() until a better solution to timer andadrian2011-10-011-0/+16
| | | | interrupt handling can be implemented.
* MIPS changes for Netlogic XLP support.jchandra2011-07-161-1/+1
| | | | | | | | | | | | | | This patch adds support for the Netlogic XLP mips64 processors in the common MIPS code. The changes are : - Add CPU_NLM processor type - Add cases for CPU_NLM, mostly were CPU_RMI is used. - Update cache flush changes for CPU_NLM - Add kernel build configuration files for xLP. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
* Use correct types and fromats for physical addressjchandra2011-02-281-8/+8
| | | | | | - Use vm_paddr_t for pa in pmap_steal_memory() - Use uintmax_t and %jx to ensure that physical address are printed correctly in cpu_startup() and pmap_bootstrap()
* Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.pluknet2011-01-211-1/+0
| | | | | | | Submitted by: perryh pluto.rain.com (previous version) Reviewed by: jhb Approved by: kib (mentor) Tested by: universe
* Make cpu_model public (otherwise there's no way to set it) and bump itimp2011-01-171-1/+4
| | | | | to 80 characters. Add hw.board to export board information, if known, from the mips kernel.
* Support for 64 bit PTEs on n32 and n64 compilation.jchandra2011-01-131-2/+3
| | | | | | | | | | | | | | | | | | | | In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version)
* Cleanup physical address and PTE types on MIPS.jchandra2011-01-131-4/+4
| | | | | | | | | | | | | | | | | | | 1. Use vm_paddr_t for physical addresses. There are a few places in the MIPS platform code where vm_offset_t is used for physical addresses, change these to use vm_paddr_t: - phys_avail[], physmem_desc[] arrays - pmap_mapdev(), page_is_managed(), is_cacheable_mem() pmap_map() args - local variables of various pmap functions 2. Change init_pte_prot() return from int to pt_entry_t, as this can be 64 bit when using 64 bit TLB entries. 3. Update printing of pt_entry_t and of vm_paddr_t to use 'j' format with uintmax_t. This will be useful later if we plan to use 64bit phsical addr on 32 bit n32 compilation. Reviewed by: imp
* o) When trying to determine whether the pcpu pointer is a managed address, checkjmallett2011-01-011-5/+17
| | | | | | | | | | | | not just that it is greater than the minimal kernel virtual address, but also that it is less than the maximal kernel virtual address. On n64 kernels, the pcpup comes out of a direct-mapped address that, with an unsigned compare, is rather greater than the minimal kernel virtual address. o) Turn the panic if interrupts are disabled in cpu_idle into a KASSERT since on other architectures it's behind INVARIANTS anyway. o) Add a check that not all interrupts are masked, too. o) Add cpu_idleclock() and cpu_activeclock() use to cpu_idle as is done on other architectures.
* - Add minidump support for FreeBSD/mipsgonzo2010-11-071-7/+1
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* Adjust the order of operations in spinlock_enter() and spinlock_exit() tojhb2010-11-051-4/+10
| | | | | | | | | | | | | | | | | | work properly with single-stepping in a kernel debugger. Specifically, these routines have always disabled interrupts before increasing the nesting count and restored the prior state of interrupts after decreasing the nesting count to avoid problems with a nested interrupt not disabling interrupts when acquiring a spin lock. However, trap interrupts for single-stepping can still occur even when interrupts are disabled. Now the saved state of interrupts is not saved in the thread until after interrupts have been disabled and the nesting count has been increased. Similarly, the saved state from the thread cannot be read once the nesting count has been decreased to zero. To fix this, use temporary variables to store interrupt state and shuffle it between the thread's MD area and the appropriate registers. In cooperation with: bde MFC after: 1 month
* Get rid of the unnecessary redirection of 'is_cacheable_mem()' toneel2010-09-171-1/+1
| | | | | | 'is_physical_memory()' through a macro. Implement 'is_cacheable_mem()' directly instead.
* Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistentneel2010-09-151-1/+1
| | | | | | with the meaning of IM bits in the status register. Reviewed by: jmallett, jchandra
* Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.jchandra2010-08-131-1/+1
| | | | | use CPU_RMI all XLR configurations. Update ident string for N32 and N64 kernels.
* Update MIPS timer code (except RMI) to utilize new MI event timermav2010-07-231-0/+2
| | | | | | infrastructure. Reviewed by: neel
* Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executivejmallett2010-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | library: o) Increase inline unit / large function growth limits for MIPS to accommodate the needs of the Simple Executive, which uses a shocking amount of inlining. o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and the Octeon SoC. o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific board numbers, specifically to support the MR320. o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd, which improperly uses an evaluation board's board number and breaks board detection at runtime. This board is sold by Portwell as the CAM-0100. o) Add support for the RTC available on some Octeon boards. o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO ports can not work unless building for n64. o) Clean up the CompactFlash driver to use Simple Executive macros and structures where possible (it would be advisable to use the Simple Executive API to set the PIO mode, too, but that is not done presently.) Also use structures from FreeBSD's ATA layer rather than structures copied from Linux. o) Print available Octeon SoC features on boot. o) Add support for the Octeon timecounter. o) Use the Simple Executive's routines rather than local copies for doing reads and writes to 64-bit addresses and use its macros for various device addresses rather than using local copies. o) Rename octeon_board_real to octeon_is_simulation to reduce differences with Cavium-provided code originally written for Linux. Also make it use the same simplified test that the Simple Executive and Linux both use rather than our complex one. o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus to use normal interrupt allocation and setup routines. o) Use the Simple Executive's bootmem facility to allocate physical memory for the kernel, rather than assuming we know which addresses we can steal. NB: This may reduce the amount of RAM the kernel reports you as having if you are leaving large temporary allocations made by U-Boot allocated when starting FreeBSD. o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes Ethernet interface naming from rgmxN to octeN. The new driver has vast improvements over the old one, both in performance and functionality, but does still have some features which have not been ported entirely and there may be unimplemented code that can be hit in everyday use. I will make every effort to correct those as they are reported. o) Support loading the kernel on non-contiguous cores. o) Add very conservative support for harvesting randomness from the Octeon random number device. o) Turn SMP on by default. o) Clean up the style of the Octeon kernel configurations a little and make them compile with -march=octeon. o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple Executive. o) Modify the Simple Executive to build on FreeBSD and to build without executive-config.h or cvmx-config.h. In the future we may want to revert part of these changes and supply executive-config.h and cvmx-config.h and access to the options contained in those files via kernel configuration files. o) Modify the Simple Executive USB routines to support getting and setting of the USB PID.
* Remove i386-ish sysctls. Also, make the bootinfo sysctl OID_AUTO.imp2010-07-151-16/+1
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* Prefer the cpuregs.h spellings of register and bit names over cpu.h.imp2010-07-141-7/+7
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* Merge jmallett@'s n64 work into HEAD - changeset 6jchandra2010-06-231-1/+1
| | | | | | | | | | | | PTE flag cleanup from http://svn.freebsd.org/base/user/jmallett/octeon - Rename PTE_xx flags to match their MIPS names - Use the new pte_set/test/clear macros uniformly, instead of a mixture of mips_pg_xxx(), pmap_pte_x() macros and direct access. - Remove unused macros and defines from pte.h and pmap.c Discussed on freebsd-mips@ Approved by: rrs(mentor), jmallett
* Merge jmallett@'s n64 work into HEAD - changeset 4jchandra2010-06-171-9/+7
| | | | | | | | | Re-write tlb operations in C with a simpler API. Update callers to use the new API. Changes from http://svn.freebsd.org/base/user/jmallett/octeon Approved by: rrs(mentor), jmallett
* This pushes all of JC's patches that I have in place. Irrs2010-05-161-1/+1
| | | | | | | | | | | am now able to run 32 cores ok.. but I still will hang on buildworld with a NFS problem. I suspect I am missing a patch for the netlogic rge driver. JC check and see if I am missing anything except your core-mask changes Obtained from: JC
* o) Eliminate the "stand" frame and its use. Use CALLFRAME_* everywhere.jmallett2010-04-191-1/+0
| | | | | | | | | | | | | | | | | o) Use <machine/asm.h> macros for register-width, etc., rather than doing it by hand in a few more assembly files. o) Reduce diffs between various bits of TLB refill code in exception.S and between interrupt processing code. o) Use PTR_* to operate on registers that are pointers (e.g. sp). o) Add and use a macro, CLEAR_PTE_SWBITS rather than using the mysteriously-named WIRED_SHIFT to select bits to truncate when loading PTEs. o) Don't doubly disable interrupts by moving zero to the status register, especially since that has the nasty side-effect of taking us out of 64-bit mode. o) Use CLEAR_STATUS to disable interrupts the first time. o) Keep SR_PX set as well as SR_[KSU]X when doing exception processing. This is the bit that determines whether 64-bit operations are allowed. o) Don't enable interrupts until configure_final(), like most other ports.
* o) Add a VM find-space option, VMFS_TLB_ALIGNED_SPACE, which searches thejmallett2010-04-181-3/+2
| | | | | | | | | | | | | | | | | | | | | address space for an address as aligned by the new pmap_align_tlb() function, which is for constraints imposed by the TLB. [1] o) Add a kmem_alloc_nofault_space() function, which acts like kmem_alloc_nofault() but allows the caller to specify which find-space option to use. [1] o) Use kmem_alloc_nofault_space() with VMFS_TLB_ALIGNED_SPACE to allocate the kernel stack address on MIPS. [1] o) Make pmap_align_tlb() on MIPS align addresses so that they do not start on an odd boundary within the TLB, so that they are suitable for insertion as wired entries and do not have to share a TLB entry with another mapping, assuming they are appropriately-sized. o) Eliminate md_realstack now that the kstack will be appropriately-aligned on MIPS. o) Increase the number of guard pages to 2 so that we retain the proper alignment of the kstack address. Reviewed by: [1] alc X-MFC-after: Making sure alc has not come up with a better interface.
* o) Use inline functions to access coprocessor 0 registers rather than externaljmallett2010-04-171-15/+5
| | | | | | | | | | | | | | | | | | | | ones implemented using assembly. o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate <machine/psl.h> as a result. o) Use intr_*() rather than *intr(), consistently. o) Use register_t instead of u_int in some trap code. o) Merge some more endian-related macros to machine/asm.h from NetBSD. o) Add PTR_LI macro, which loads an address with the correct sign-extension for a pointer. o) Restore interrupts when bailing out due to an excessive IRQ in nexus_setup_intr(). o) Remove unused functions from psraccess.S. o) Enter temporary virtual entries for large memory access into the page tables rather than simply hoping they stay resident in the TLB and we don't need to do a refill for them. o) Abstract out large memory mapping setup/teardown using some macros. o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just like we do when we can use the direct map.
* o) Remove code related to VM_ALLOC_WIRED_TLB_PG_POOL, VM_KERNEL_ALLOC_OFFSETjmallett2010-04-171-4/+0
| | | | and floating pages. They are unused and unsupported.
* SMP support for the mips port.neel2010-02-091-14/+17
| | | | | | | The platform that supports SMP currently is a SWARM with a dual-core Sibyte processor. The kernel config file to use is SWARM_SMP. Reviewed by: imp, rrs
* Provide access to pcpu structures for SMP kernels.neel2010-01-301-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic idea is to use a the same virtual address as a window onto distinct physical memory locations - one per processor. The physical address that you access through this mapping depends on which cpu you are currently executing on. We can now use the same virtual address on any processor to access its per-cpu area. The details are: - The virtual address for 'struct pcpu *pcpup' is obtained by stealing 2 pages worth of KVA in pmap_bootstrap(). - The mapping from the constant virtual address to a distinct physical page is done in cpu_pcpu_init() through a wired TLB entry. - A side-effect of this is that we reserve 2 pages worth of memory for the pcpu but in reality it needs much less than that. The unused memory is now used as the boot stack for the BSP and APs. Remove SMP-specific bits from locore.S. The plan is to use a separate mpboot.S for AP bootstrap. Discussed on: freebsd-mips Approved by: imp (mentor)
* - Introduce kernel_kseg0_end variable that marks first address in KSEG0gonzo2010-01-241-0/+33
| | | | | | | | | | | available for use. All data below this address considered to be used by kernel. Along with kernel own data it might be symbol tables prepeared by trampoline code, boot loader service data passed for further analysis by kernel, etc... By default kernel_kseg0_end points to the end of loaded kernel. - Introduce mips_postboot_fixup function. It checks for symbol information copied by ELF trampoline and passes it to KDB
* Create a method of last resort for rebooting the mips processor: jumpimp2010-01-221-0/+12
| | | | | to the reset vector. This works for many SoCs where other reset hardware is either missing or unknown.
* Remove duplicate bootverbose increment.rpaulo2010-01-221-1/+0
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* Make sure that interrupts are enabled when thread0 is running.neel2010-01-201-1/+3
| | | | Approved by: imp (mentor)
* Merge from projects/mips to head by hand:imp2010-01-101-31/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sorry for the huge firehose on this commit, it would be too tedious to do file by file r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r201880 | neel | 2010-01-08 19:17:14 -0700 (Fri, 08 Jan 2010) | 7 lines Compute the target of the jump in the 'J' and 'JAL' instructions correctly. The 256MB segment is formed by taking the top 4 bits of the address of the instruction in the "branch delay" slot as opposed to the 'J' or 'JAL' instruction itself. r201845 | imp | 2010-01-08 15:48:21 -0700 (Fri, 08 Jan 2010) | 2 lines Centralize initialization of pcpu, and set curthread early... r201770 | neel | 2010-01-07 22:53:11 -0700 (Thu, 07 Jan 2010) | 4 lines Add a DDB command "show pcb" to dump out the contents of a thread's PCB. r201631 | neel | 2010-01-05 23:42:08 -0700 (Tue, 05 Jan 2010) | 5 lines Remove all CFE-specific code from locore.S. The CFE entrypoint initialization is now done in platform-specific code. r201563 | neel | 2010-01-04 23:58:54 -0700 (Mon, 04 Jan 2010) | 6 lines This change increases the size of the kernel stack for thread0 from PAGE_SIZE to (2 * PAGE_SIZE). It depends on the memory allocated by pmap_steal_memory() being aligned to a PAGE_SIZE boundary. r200656 | imp | 2009-12-17 16:55:49 -0700 (Thu, 17 Dec 2009) | 7 lines Place holder ptrace mips module. Not entirely sure what's required here yet, so I've not connected it to the build. I think that we'll need to move something into the processor specific part of the mips port by requiring mips_cpu_ptrace or platform_cpu_ptrace be provided by the ports to get/set processor specific registers, ala SSE registers on x86. r200342 | imp | 2009-12-09 18:42:44 -0700 (Wed, 09 Dec 2009) | 4 lines app_descriptor_addr is unused (I know it is referened still). And unnecessary since we pass in a3 unmodified to platform_start. Eliminate it from here and kill one more TARGET_OCTEON in the process. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199755 | imp | 2009-11-24 09:53:58 -0700 (Tue, 24 Nov 2009) | 5 lines looks like there's more to this patch than just this one file. I'll leave it to neel@ to get all the relevant pieces into the tree. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. # for the most part, we need to enhance infrastructure to obviate the need # for such an intrusive option. r199753 | imp | 2009-11-24 09:30:29 -0700 (Tue, 24 Nov 2009) | 3 lines Remove a comment that's bogus. Include opt_cputype.h since TARGET_OCTEON moved there. r199752 | imp | 2009-11-24 09:29:23 -0700 (Tue, 24 Nov 2009) | 4 lines Make sure kstack0 is page aligned. # this may have been from neel@ for the sibyte stuff r199742 | imp | 2009-11-24 01:35:11 -0700 (Tue, 24 Nov 2009) | 8 lines Move the hard-wiring of the dcache on octeon outside of the if statement. When no caches support was added, it looks like TARGET_OCTEON was bogusly moved inside the if. Also, include opt_cputype.h to make TARGET_OCTEON actually active. # now we die in pmap init somewhere... Most likely because 32MB of RAM is # too tight given the load address we're using. r199741 | imp | 2009-11-24 01:21:48 -0700 (Tue, 24 Nov 2009) | 2 lines TARGET_OCTEON reqiures opt_cputype.h. r199736 | imp | 2009-11-24 00:40:38 -0700 (Tue, 24 Nov 2009) | 2 lines Prefer ANSI spellings of uintXX_t, etc. r199598 | imp | 2009-11-20 09:30:35 -0700 (Fri, 20 Nov 2009) | 3 lines Horrible kludge to make octeon32 work. I think a better way is to move the generic code into the config files.... r199597 | imp | 2009-11-20 09:27:50 -0700 (Fri, 20 Nov 2009) | 4 lines cast vaddr to uintptr_t before casting it to a bus_space_handle_t. # I'm sure this indicates a problem, but I'm not sure what... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r199246 | neel | 2009-11-13 02:24:09 -0700 (Fri, 13 Nov 2009) | 10 lines Make pmap_copy_page() L2-cache friendly by doing the copy through the cacheable window on physical memory (KSEG0). On the Sibyte processor going through the uncacheable window (KSEG1) bypasses both L1 and L2 caches so we may end up with stale contents in the L2 cache. This also makes it consistent with the rest of the function that uses cacheable mappings to copy pages. Approved by: imp (mentor) r198842 | gonzo | 2009-11-02 23:42:55 -0700 (Mon, 02 Nov 2009) | 3 lines - Handle errors when adding children to nexus. This sittuation might occure when there is dublicate of child's entry in hints r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198569 | neel | 2009-10-28 23:18:02 -0600 (Wed, 28 Oct 2009) | 5 lines Deal with overflow of the COUNT register correctly. The 'cycles_per_hz' has nothing to do with the rollover. r198550 | imp | 2009-10-28 11:03:20 -0600 (Wed, 28 Oct 2009) | 3 lines Remove useless for statement. i isn't used after it. Remove needless braces. r198534 | gonzo | 2009-10-27 21:34:05 -0600 (Tue, 27 Oct 2009) | 8 lines - Fix busdma sync: dcache invalidation operates on cache line aligned addresses and could modify areas of memory that share the same cache line at the beginning and at the ending of the buffer. In order to prevent a data loss we save these chunks in temporary buffer before invalidation and restore them afer it. Idea suggested by: cognet r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198530 | gonzo | 2009-10-27 17:45:48 -0600 (Tue, 27 Oct 2009) | 3 lines - Replace stubs with actual cache info - minor style(9) fix r198355 | neel | 2009-10-21 22:35:32 -0600 (Wed, 21 Oct 2009) | 11 lines Remove redundant instructions from tlb.S The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been initialized at that point. It worked correctly because we subsequently did the right thing and initialized TLB_HI correctly. The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same thing 2 instructions down. r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198264 | neel | 2009-10-19 22:36:08 -0600 (Mon, 19 Oct 2009) | 5 lines Fix a bug where we would think that the L1 instruction and data cache are present even though the line size field in the CP0 Config1 register is 0. r198208 | imp | 2009-10-18 09:21:48 -0600 (Sun, 18 Oct 2009) | 3 lines Get the PC from the trap frame, since it isn't saved as part of the pcb regs. r198205 | imp | 2009-10-18 08:55:55 -0600 (Sun, 18 Oct 2009) | 3 lines Use correct signature for MipsEmulateBranch. The other one doesn't work for 64-bit compiles. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197796 | gonzo | 2009-10-05 17:19:51 -0600 (Mon, 05 Oct 2009) | 2 lines - Revert part of r197685 because this change leads to wrong data in cache. r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r197014 | imp | 2009-09-08 21:57:10 -0600 (Tue, 08 Sep 2009) | 2 lines Ugly hack to get this to compile. I'm sure there's a better way... r197013 | imp | 2009-09-08 21:54:55 -0600 (Tue, 08 Sep 2009) | 2 lines First half of making this 64-bit clean: fix prototypes. r196988 | gonzo | 2009-09-08 13:15:29 -0600 (Tue, 08 Sep 2009) | 2 lines - MFC from head@196987 r196313 | imp | 2009-08-17 06:14:40 -0600 (Mon, 17 Aug 2009) | 2 lines suword64 and csuword64. Needed by ELF64 stuff... r196266 | imp | 2009-08-15 16:51:11 -0600 (Sat, 15 Aug 2009) | 5 lines (1) Fix a few 32/64-bit bugs. (2) Also, always allocate 2 pages for the stack to optimize TLB usage. Submitted by: neel@ (2) r196265 | imp | 2009-08-15 16:48:09 -0600 (Sat, 15 Aug 2009) | 2 lines Various 32/64-bit confusion cleanups. r196264 | imp | 2009-08-15 16:45:46 -0600 (Sat, 15 Aug 2009) | 6 lines (1) Some CPUs have a range to map I/O cyces on the pci bus. So allow them to work by allowding the nexus to assign ports. (2) Remove some Octeon junk that shouldn't be necessary. Submitted by: neel@ (#1) for SB1 port. r196061 | gonzo | 2009-08-04 11:32:55 -0600 (Tue, 04 Aug 2009) | 2 lines - Use register_t for registers values r195984 | gonzo | 2009-07-30 17:48:29 -0600 (Thu, 30 Jul 2009) | 4 lines - Properly unwind stack for functions with __noreturn__ attribute Submitted by: Neelkanth Natu <neelnatu@yahoo.com> r195983 | gonzo | 2009-07-30 17:29:59 -0600 (Thu, 30 Jul 2009) | 4 lines - mark map as coherent if requested by flags - explicitly set memory allocation method in map flags instead of duplicating conditions for malloc/contigalloc r195584 | imp | 2009-07-10 13:09:34 -0600 (Fri, 10 Jul 2009) | 3 lines Use PTR_* macros for pointers, and not potentially mips64 unsafe operations. r195583 | imp | 2009-07-10 13:08:48 -0600 (Fri, 10 Jul 2009) | 2 lines Use PTR_* macros to deal with pointers. r195579 | imp | 2009-07-10 13:04:32 -0600 (Fri, 10 Jul 2009) | 2 lines use ta0-ta3 rather than t4-t7 for n32/n64 goodness. r195511 | gonzo | 2009-07-09 13:02:17 -0600 (Thu, 09 Jul 2009) | 3 lines - Ooops, this debug code wasn't supposed to get into final commit. My appologises. r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195438 | imp | 2009-07-08 00:00:18 -0600 (Wed, 08 Jul 2009) | 2 lines Turns out this code was right, revert last change. r195429 | gonzo | 2009-07-07 13:55:09 -0600 (Tue, 07 Jul 2009) | 5 lines - Move dpcpu initialization to mips_proc0_init. It's more appropriate place for it. Besides dpcpu_init requires pmap module to be initialized and calling it int pmap.c hangs the system r195399 | imp | 2009-07-06 01:49:24 -0600 (Mon, 06 Jul 2009) | 2 lines Prefer uintptr_t to int cast here. r195398 | imp | 2009-07-06 01:48:31 -0600 (Mon, 06 Jul 2009) | 3 lines Better types for 64-bit compatibility. Use %p and cast to void * and prefer uintptr_t to other int-type casts. r195397 | imp | 2009-07-06 01:47:39 -0600 (Mon, 06 Jul 2009) | 2 lines No need to force mips32 here. r195396 | imp | 2009-07-06 01:46:13 -0600 (Mon, 06 Jul 2009) | 3 lines Pass in the uint64 value, rather than a pointer to it. that's what the function expects... r195395 | imp | 2009-07-06 01:45:02 -0600 (Mon, 06 Jul 2009) | 3 lines Use ta0 instead of t4 and ta1 instead of t5. These map to the same registers on O32 builds, but t4 and t5 don't exist on N32 or N64. r195394 | imp | 2009-07-06 01:43:50 -0600 (Mon, 06 Jul 2009) | 3 lines Use better casts for passing the small integer as a pointer here. Basically, replace int with uintptr_t. r195393 | imp | 2009-07-06 01:42:54 -0600 (Mon, 06 Jul 2009) | 5 lines (1) Improvements for SB1. only allow real memory to be accessed. (2) make compile n64 by using more-proper casts. Submitted by: Neelkanth Natu (1) r195373 | imp | 2009-07-05 09:23:54 -0600 (Sun, 05 Jul 2009) | 5 lines (1) Use PTR_LA rather than bare la for N64 goodness (it is dla there) (2) SB1 needs COHERENT policy, not cached for the config register Submitted by: (2) Neelkanth Natu r195372 | imp | 2009-07-05 09:22:22 -0600 (Sun, 05 Jul 2009) | 3 lines use "PTR_LA" in preference to a bare la so it translates to dla on 64-bit ABIs. r195371 | imp | 2009-07-05 09:21:35 -0600 (Sun, 05 Jul 2009) | 6 lines Now that we define atomic_{load,store}_64 inline in atomic.h, we don't need to define them here for the !N64 case. We now define atomic_readandclear_64 in atomic.h, so no need to repeat it here. r195364 | imp | 2009-07-05 09:10:07 -0600 (Sun, 05 Jul 2009) | 5 lines use %p in preference to 0x%08x for printing register_t values. Cast them to void * first. This neatly solves the "how do I print a register_t" problem because sizeof(void *) is always the same as sizeof(register_t), afaik. r195353 | imp | 2009-07-05 00:46:54 -0600 (Sun, 05 Jul 2009) | 6 lines Publish PAGE_SHIFT to assembler # we should likely phase out PGSHIFT Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195334 | imp | 2009-07-03 21:22:34 -0600 (Fri, 03 Jul 2009) | 6 lines Move from using the lame invalid address I chose when trying to get Octeon going... Turns out that you get tlb shutdowns with this... Use PGSHIFT instead of PAGE_SHIFT. Submitted by: Neelkanth Natu r195147 | gonzo | 2009-06-28 15:01:00 -0600 (Sun, 28 Jun 2009) | 2 lines - Replace casuword and casuword32 stubs with proper implementation r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195127 | gonzo | 2009-06-27 17:01:35 -0600 (Sat, 27 Jun 2009) | 4 lines - Make cpu_set_upcall_kse conform MIPS ABI. T9 should be the same as PC in subroutine entry point - Preserve interrupt mask r194938 | gonzo | 2009-06-24 20:15:04 -0600 (Wed, 24 Jun 2009) | 3 lines - Invalidate cache in pmap_qenter. Fixes corruption of data that comes through pipe (may be other bugs) r194505 | gonzo | 2009-06-19 13:02:40 -0600 (Fri, 19 Jun 2009) | 5 lines - Keep interrupts mask intact by RESTORE_CPU in MipsKernGenException trap() function re-enables interrupts if exception happened with interrupts enabled and therefor status register might be modified by interrupt filters r194277 | gonzo | 2009-06-15 20:36:21 -0600 (Mon, 15 Jun 2009) | 2 lines - Remove debug printfs r194275 | gonzo | 2009-06-15 19:43:33 -0600 (Mon, 15 Jun 2009) | 2 lines - Handle KSEG0/KSEG1 addresses for /dev/mem as well. netstat requires it r193491 | gonzo | 2009-06-05 03:21:03 -0600 (Fri, 05 Jun 2009) | 6 lines - Status register should be set last in RESTORE_CPU in order to prevent race over k0, k1 registers. - Update interrupts mask in saved status register for MipsUserIntr and MipsUserGenException. It might be modified by intr filter or ithread. r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192794 | gonzo | 2009-05-26 00:20:50 -0600 (Tue, 26 May 2009) | 5 lines - Preserve INT_MASK fields in Status register across context switches. They should be modified only by interrupt setup/teardown and pre_ithread/post_ithread functions r192793 | gonzo | 2009-05-26 00:02:38 -0600 (Tue, 26 May 2009) | 2 lines - Remove erroneus "break" instruction, it was meant for debug r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192791 | gonzo | 2009-05-25 23:59:05 -0600 (Mon, 25 May 2009) | 7 lines - Provide proper pre_ithread/post_ithread functions for both hard and soft interrupts - Do not handle masked interrupts - Do not write Cause register because most bytes are read-only and writing the same byte to RW fields are pointless. And in case of software interrupt utterly wrong r192664 | gonzo | 2009-05-23 13:42:23 -0600 (Sat, 23 May 2009) | 4 lines - cpu_establish_hardintr modifies INT_MASK of Status register, so we should use disableintr/restoreintr that modifies only IE bit. r192655 | gonzo | 2009-05-23 12:00:20 -0600 (Sat, 23 May 2009) | 6 lines - Remove stale comments - Replace a1 with k1 to while restoring context. a1 was there by mistake, interrupts are disabled at this point and it's safe to use k0, k1. This code never was reached beacasue current Status register handling prevented interrupta from user mode. r192496 | gonzo | 2009-05-20 17:07:10 -0600 (Wed, 20 May 2009) | 4 lines - Invalidate caches for respective areain KSEG0 in order to prevent further overwriting of KSEG1 data with writeback. r192364 | gonzo | 2009-05-18 20:43:21 -0600 (Mon, 18 May 2009) | 6 lines - Cleanup ticker initialization code. For some MIPS cpu Counter register increments only every second cycle. The only timing references for us is Count value. Therefore it's better to convert frequencies related to it and use them. Besides cleanup this commit fixes twice more then requested sleep interval problem. r192176 | gonzo | 2009-05-15 20:34:03 -0600 (Fri, 15 May 2009) | 3 lines - Add informational title for cache info lines to separate them from environment variables dump r192119 | gonzo | 2009-05-14 15:26:07 -0600 (Thu, 14 May 2009) | 3 lines - Off by one check fix. Check for last address in region to fit in KSEG1 r191841 | gonzo | 2009-05-05 20:55:43 -0600 (Tue, 05 May 2009) | 5 lines - Use index ops in order to avoid TLBMiss exceptions when flushing caches on mapping removal - Writeback all VA for page that is being copied in pmap_copy_page to guaranty up-to-date data in SDRAM r191613 | gonzo | 2009-04-27 20:59:18 -0600 (Mon, 27 Apr 2009) | 4 lines - When destroying va -> pa mapping writeback all caches or we may endup with partial page content in SDRAM - style(9) fix r191583 | gonzo | 2009-04-27 12:46:57 -0600 (Mon, 27 Apr 2009) | 5 lines - Use new spacebus - Be a bit more verbose on failures - style(9) fixes - Use default rid value of 0 instead of MIPS_MEM_RID (0x20) r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191453 | gonzo | 2009-04-23 23:28:44 -0600 (Thu, 23 Apr 2009) | 4 lines Fix cut'n'paste code. cfg3 should get the value of selector 3 Spotted by: thompa@ r191452 | gonzo | 2009-04-23 22:18:16 -0600 (Thu, 23 Apr 2009) | 2 lines - Print supported CPU capabilities during stratup r191448 | gonzo | 2009-04-23 21:38:51 -0600 (Thu, 23 Apr 2009) | 2 lines - Fix whitespace to conform style(9) r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. r191083 | gonzo | 2009-04-14 19:47:52 -0600 (Tue, 14 Apr 2009) | 4 lines - Cleanout stale #ifdef'ed chunk of code - Fix whitespaces - Explicitly undefine NEXUS_DEBUG flag r191079 | gonzo | 2009-04-14 16:53:22 -0600 (Tue, 14 Apr 2009) | 2 lines - Revert changes accidentally killed by merge operation ------------------------------------------------------------------------ r187512 | gonzo | 2009-01-20 22:49:30 -0700 (Tue, 20 Jan 2009) | 4 lines - Check if maddr/msize hints are there before setting hinted resources to device - Check for irq hint too r187418 | gonzo | 2009-01-18 19:37:10 -0700 (Sun, 18 Jan 2009) | 4 lines - Add trampoline stuff for bootloaders that do not support ELF - Replace arm'ish KERNPHYSADDR/KERNVIRTADDR with KERNLOADADDR/TRAMPLOADADDR and clean configs
* Unbreak booting of FreeBSD/mips by merging r195429 from projects/mips:gonzo2009-11-091-0/+3
| | | | | | | - Move dpcpu initialization to mips_proc0_init. It's more appropriate place for it. Besides dpcpu_init requires pmap module to be initialized and calling it int pmap.c hangs the system
* Add cpu_flush_dcache() for use after non-DMA based I/O so that amarcel2009-05-181-0/+10
| | | | | | | | | | | | | | | | | | | | | possible future I-cache coherency operation can succeed. On ARM for example the L1 cache can be (is) virtually mapped, which means that any I/O that uses temporary mappings will not see the I-cache made coherent. On ia64 a similar behaviour has been observed. By flushing the D-cache, execution of binaries backed by md(4) and/or NFS work reliably. For Book-E (powerpc), execution over NFS exhibits SIGILL once in a while as well, though cpu_flush_dcache() hasn't been implemented yet. Doing an explicit D-cache flush as part of the non-DMA based I/O read operation eliminates the need to do it as part of the I-cache coherency operation itself and as such avoids pessimizing the DMA-based I/O read operations for which D-cache are already flushed/invalidated. It also allows future optimizations whereby the bcopy() followed by the D-cache flush can be integrated in a single operation, which could be implemented using on-chips DMA engines, by-passing the D-cache altogether.
* Remove unused variable.imp2009-01-161-14/+4
| | | | Minor style nits.
* Reduce diffs to p4 that were the result of a mismerge on my part.imp2009-01-151-2/+5
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* MFp4:imp2009-01-151-7/+2
| | | | | Remove Maxmem. It isn't used elsewhere in the system at this point... realmem is used instead.
* Call platform_reset() instead of looping forever on reboot.imp2009-01-151-3/+3
| | | | | # We likely need to have a default one of these that jumps to the rom boot # address that's defined in the MIPS ISA.
* Reverse order of dumpsys and cpu_idle_wakeup to reduce diffs to p4.imp2009-01-151-6/+6
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* MFp4:imp2009-01-151-117/+0
| | | | Remove #if'd 0 code. It is interfering with other diffs.
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