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* Garbage collect unused prototype for clockintr().rwatson2016-05-201-2/+0
| | | | MFC after: 3 days
* When attempting to satisfy mmap() requests for superpage alignment onrwatson2016-04-301-0/+2
| | | | | | | | | | 64-bit MIPS, use superpage rather than physical-segment constants, or we may improperly fail to apply suitable alignment -- yet still allow mmap() to appear to succeed. Reviewed by: sson MFC after: 1 week Sponsored by: DARPA, AFRL
* Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machineandrew2016-04-152-3/+3
| | | | | | | independent code that needs to know about INTRNG such as PCI drivers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
* Make NIRQ configurable for MIPSsgalabov2016-04-151-2/+6
| | | | | | | Submitted by: kan Reviewed by: kan Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D5964
* Define PCI_RES_BUS for MIPS.sgalabov2016-04-121-0/+3
| | | | | | | This is done as part of the work on D5908, but as a separate commit. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD
* POSIX states that #include <signal.h> shall make both mcontext_t andkib2016-02-121-5/+5
| | | | | | | | | | | | | | | | | | | | ucontext_t available. Our code even has XXX comment about this. Add a bit of compliance by moving struct __ucontext definition into sys/_ucontext.h and including it into signal.h and sys/ucontext.h. Several machine/ucontext.h headers were changed to use namespace-safe types (like uint64_t->__uint64_t) to not depend on sys/types.h. struct __stack_t from sys/signal.h is made always visible in private namespace to satisfy sys/_ucontext.h requirements. Apparently mips _types.h pollutes global namespace with f_register_t type definition. This commit does not try to fix the issue. PR: 207079 Reported and tested by: Ting-Wei Lan <lantw44@gmail.com> Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Missing commit - remove MIPS fdt bus space.adrian2016-02-111-1/+0
| | | | Differential Revision: https://reviews.freebsd.org/D5184
* Remove bus space fdt for MIPS.adrian2016-02-111-1/+1
| | | | | | | | This was originall done by kan@. Submitted by: Stanislav Galabov <sgalabov@gmail.com> Reviewed by: kan Differential Revision: https://reviews.freebsd.org/D5184
* Begin the MIPS_INTRNG support.adrian2016-02-112-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a prelude to intr-ng support for MIPS boards that need it - notably the CI20 port from kan@ that's upcoming, but also work that Stanislav is doing for the Mediatek platforms. This is the initial platform dependent bits in include/intr.h, some #defines for the nexus code for the intrng initialisation/runtime bits, some changed naming (which I'll fix later to be the same, much like what I did for ARM intr-ng) in exception.S, and the first cut at a PIC. Stanislav and I refactored out the common code for intrng support, so the mips intrng definitions are quite small (sys/mips/include/intr.h.) This is all work done by kan@, which stanislav has been cherry picking into common code for his mediatek chipset work. Tested: * Carambola2 - no regressions (not intr-ng though!) Submitted by: Stanislav Galabov <sgalabov@gmail.com> Reviewed by: kan (original author) Differential Revision: https://reviews.freebsd.org/D5182
* Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction foradrian2016-02-021-5/+27
| | | | | | | | | | | | | | | | clearing hazards. This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K (somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to this list. Also, for the cases of MIPS coherent processing systems (currently 1004K, 1074K, interAptiv and proAptiv) - define proper CCA attributes. Submitted by: Stanislav Galabov <sgalabov@gmail.com> Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D5078
* Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx optionsadrian2016-02-023-5/+5
| | | | | | | | | | | | | | | | | | | | | | | This revision does the following renames: CPU_MIPS24KC -> CPU_MIPS24K CPU_MIPS74KC -> CPU_MIPS74K CPU_MIPS1004KC -> CPU_MIPS1004K It also adds the following new CPU_MIPSxxx options: CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the MIPSxxxxK CPU has no FPU. It would be better if the CPUs are named after their standard functionalities only and the presence or absence of FPU can then be controlled via the CPU_HAVEFPU option. I will send out another dependent revision that moves MIPS 32 r2 and r3 CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP. Submitted by: Stanislav Galabov <sgalabov@gmail.com> Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D5077
* Shift saved floating point registers up in jmp_buf.brooks2016-01-201-14/+15
| | | | | | | | sigmask_t is 128-bits so requires two slots. Approved by: CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc) MFC after: 1 week Sponsored by: DARPA, AFRL
* Begin the initial support for the mips1004kc core.adrian2015-12-242-2/+14
| | | | | | | | | | | | | * add build option; * add initial coherence manager config register bits; * use the right hazard instruction (ehb); * add page attributes. Tested: * MT7621A SoC (not yet in-tree) Submitted by: Stanislav Galabov <sgalabov@gmail.com>
* [mips] Add TLB pagemask probing code, and print out the allowable page sizes.adrian2015-12-222-0/+14
| | | | | | This is from Stacey's work on larger kernel stack sizes for MIPS. Thanks! Submitted by: sson
* Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.hian2015-12-201-3/+0
| | | | | | is what includes machine/ofw_machdep.h. Don't declare OF_decode_addr(); it isn't implemented yet on mips and the declaration for it is about to be commonized into openfirm.h.
* Introduce a new mechanism for relocating virtual pages to a new physicalalc2015-12-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | address and use this mechanism when: 1. kmem_alloc_{attr,contig}() can't find suitable free pages in the physical memory allocator's free page lists. This replaces the long-standing approach of scanning the inactive and inactive queues, converting clean pages into PG_CACHED pages and laundering dirty pages. In contrast, the new mechanism does not use PG_CACHED pages nor does it trigger a large number of I/O operations. 2. on 32-bit MIPS processors, uma_small_alloc() and the pmap can't find free pages in the physical memory allocator's free page lists that are covered by the direct map. Tested by: adrian 3. ttm_bo_global_init() and ttm_vm_page_alloc_dma32() can't find suitable free pages in the physical memory allocator's free page lists. In the coming months, I expect that this new mechanism will be applied in other places. For example, balloon drivers should use relocation to minimize fragmentation of the guest physical address space. Make vm_phys_alloc_contig() a little smarter (and more efficient in some cases). Specifically, use vm_phys_segs[] earlier to avoid scanning free page lists that can't possibly contain suitable pages. Reviewed by: kib, markj Glanced at: jhb Discussed with: jeff Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D4444
* Correct the CONFIG0_VI value. According toimp2015-12-111-1/+1
| | | | | | | | | | | | http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the config0 word, not bit 2. This should fix virtually indexed caches (relatively new in the MIPS world, so no current platforms used this and current code just uses it as an optimization). It was causing false positives on newer platforms that default to large values for the kseg0 cache coherency attribute. Submitted by: Stanislav Galabov PR: 205249
* mips74k: use cache-writeback for memory, not writethrough.adrian2015-10-311-1/+1
| | | | | | | | | | | | | | | | | | | When I ported this code from netbsd I was .. slightly mips74k greener. I used writethrough because (a) it's what netbsd did, and (b) if I used writethrough then things "didn't work." Fast-forward a couple years, more MIPS hacking and a whole lot more understanding of the bus APIs (the last few commits notwithstanding; it's been a long week, ok?) and I have this working for arge, argemdio, spi and ath. Hans has it working for USB. The ath barrier code will come in a later commit. This gets the routing throughput up from 220mbit -> 337mbit. I'm sure the bridging throughput will be similarly improved. Tested: * QCA955x SoC, routing workload.
* Switch from a stub to a real implementation of pmap_page_set_attr() for mips,ian2015-10-211-1/+2
| | | | | | | and implement support for VM_MEMATTR_UNCACHEABLE. This will be used in upcoming changes to support BUS_DMA_COHERENT in bus_dmamem_alloc(). Reviewed by: adrian, imp
* Rationalize BSD license on sys/*/include/in_cksum.hemaste2015-08-051-1/+1
| | | | | | | Remove the advertising clause from the Regents of the University of California's license, per the letter dated July 22, 1999. Update clause numbering.
* Rationalize BSD license on sys/*/include/float.hemaste2015-08-051-1/+1
| | | | | | | Remove the advertising clause from the Regents of the University of California's license, per the letter dated July 22, 1999. Update clause numbering.
* Add the atomic_thread_fence() family of functions with intent tokib2015-07-081-0/+28
| | | | | | | | | | | | | | | | | | | | | | | provide a semantic defined by the C11 fences with corresponding memory_order. atomic_thread_fence_acq() gives r | r, w, where r and w are read and write accesses, and | denotes the fence itself. atomic_thread_fence_rel() is r, w | w. atomic_thread_fence_acq_rel() is the combination of the acquire and release in single operation. Note that reads after the acq+rel fence could be made visible before writes preceeding the fence. atomic_thread_fence_seq_cst() orders all accesses before/after the fence, and the fence itself is globally ordered against other sequentially consistent atomic operations. Reviewed by: alc Discussed with: bde Sponsored by: The FreeBSD Foundation MFC after: 3 weeks
* Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.alc2015-06-081-3/+2
| | | | | | Differential Revision: https://reviews.freebsd.org/D2712 Reviewed by: kib Sponsored by: EMC / Isilon Storage Division
* Similarly to other architecture, add the include for cpufunc.h which isbz2015-05-281-0/+1
| | | | needed for pte.h by vmstat to resolve MIPS_CCA_UNCACHED.
* Increment the vm stats "v_intr" counter so the global system interruptadrian2015-05-161-0/+1
| | | | | | | | statistics work again. I'm not sure why/when this broke, only that it used to work fine. This commit is brought to you by Maker Faire Bay Area 2015.
* Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h>jhb2015-04-081-1/+3
| | | | | | | | | | | | | | | and export them to userland. - Define __HAVE_REG32 on platforms that define a reg32 structure and check for this in <sys/procfs.h> to control when to export prstatus32, etc. - Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures. libbfd looks for these types, and having them fixes 'gcore' in gdb of a 32-bit process on a 64-bit platform. - Use the structure definitions from <sys/procfs.h> in gcore's elf32 core dump code instead of duplicating the definitions. Differential Revision: https://reviews.freebsd.org/D2142 Reviewed by: kib, nathanw (powerpc bits) MFC after: 1 week
* Add 64 byte linesize cache flushing routines for L1 instruction, L1 databr2015-03-262-11/+75
| | | | | | and L2 data caches. Sponsored by: HEIF5
* Add 128-byte cache flushing routines.br2015-01-201-2/+0
| | | | | Leave CNMIPS untouched as these functions depends on config2 register.
* Factor out duplicated code from dumpsys() on each architecture into genericmarkj2015-01-072-0/+77
| | | | | | | | | | | | | | code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly identical and simply redefine a number of constants and helper subroutines; a generic implementation will make it easier to implement features around kernel core dumps. This change does not alter any minidump code and should have no functional impact. PR: 193873 Differential Revision: https://reviews.freebsd.org/D904 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Reviewed by: jhibbits (earlier version) Sponsored by: EMC / Isilon Storage Division
* Update ELF headers to include additional definesemaste2015-01-021-29/+0
| | | | | | | | | | | | | | The elftoolchain project includes these additional defines for various userland programs. Given that arch-specific defines are still interesting in the context of userland programs reading or writing ELF metadata, they should be included in top-level ELF headers. Remove duplicate defines from ARM and MIPS elf headers. Submitted by: will (initial version) Reviewed by: imp, will Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D844
* The physical memory allocator supports the use of distinct free lists foralc2014-12-311-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | managing pages from different address ranges. Generally speaking, this feature is used to increase the likelihood that physical pages are available that can meet special DMA requirements or can be accessed through a limited-coverage direct mapping (e.g., MIPS). However, prior to this change, the configuration of the free lists was static, i.e., it was determined at compile time. Consequentally, free lists could be created for address ranges that held no actual pages, for example, on 32-bit MIPS- based systems with 512 MB or less of physical memory. This change makes the creation of the free lists dynamic, i.e., it is based on the available physical memory at boot time. On 64-bit x86-based systems with 64 GB or more of physical memory, create free lists for managing pages with physical addresses below 4 GB. This change is to address reported problems with initializing devices that require the allocation of physical pages below 4 GB on some systems with 128 GB or more of physical memory. PR: 185727 Differential Revision: https://reviews.freebsd.org/D1274 Reviewed by: jhb, kib MFC after: 3 weeks Sponsored by: EMC / Isilon Storage Division
* Correct the functions declaration.br2014-11-231-8/+8
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* Add FPU support for MIPS setjmp(3)/longjmp(3).brooks2014-11-211-0/+14
| | | | | | | | | | | | | This change saves/restores the callee-saved MIPS floating point registers as documented by the o32/n32/n64 spec ("MIPSpro N32 ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3), setjmp(3) and longjmp(3) C library functions. This is only included when the C library is built with hardware floating point support (or when "SOFTFLOAT" is not defined). Submitted by: sson MFC after: 1 month Sponsored by: DARPA, AFRL
* Add L2-cache writeback/flush operations. Supported 32,128-byte line-size,br2014-11-203-0/+23
| | | | | | | | else ignored. Cavium Networks also ignored as it has non-standard config registers. Obtained from: NetBSD Sponsored by: DARPA, AFRL
* Add fueword(9) and casueword(9) functions. They are like fuword(9)kib2014-10-281-0/+4
| | | | | | | | | | | | | | | | | and casuword(9), but do not mix value read and indication of fault. I know (or remember) enough assembly to handle x86 and powerpc. For arm, mips and sparc64, implement fueword() and casueword() as wrappers around fuword() and casuword(), which means that the functions cannot distinguish between -1 and fault. On architectures where fueword() and casueword() are native, implement fuword() and casuword() using fueword() and casuword(), to reduce assembly code duplication. Sponsored by: The FreeBSD Foundation Tested by: pho MFC after: 2 weeks (ia64 needs treating)
* Pass up the error status of minidumpsys() to its callers.markj2014-10-081-1/+1
| | | | | | PR: 193761 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Sponsored by: EMC / Isilon Storage Division
* style(9)glebius2014-09-071-4/+3
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* Implement local sfbuf_map and sfbuf_unmap for MIPS32.adrian2014-09-062-0/+20
| | | | | | | The pre-rework behaviour was not to keep the cached mappings around after the sfbuf was used but instead to recycle said mappings. PR: kern/193400
* Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.cglebius2014-08-052-51/+7
| | | | | | | | | | | | | | | The MD allocators were very common, however there were some minor differencies. These differencies were all consolidated in the MI allocator, under ifdefs. The defines from machine/vmparam.h turn on features required for a particular machine. For details look in the comment in sys/sf_buf.h. As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have machine/sf_buf.h, which is usually quite small. Tested by: glebius (i386), tuexen (arm32), kevlo (arm32) Reviewed by: kib Sponsored by: Netflix Sponsored by: Nginx, Inc.
* Add missing definition of ELF_MACHINE_OK, now used by gcore(1).marcel2014-07-261-0/+2
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* Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4tijl2014-04-011-1/+1
| | | | | | -fms-extensions. MFC after: 2 weeks
* Update NetBSD Foundation copyrights to 2-clause BSDemaste2014-03-181-7/+0
| | | | | | | | | | | The NetBSD Foundation states "Third parties are encouraged to change the license on any files which have a 4-clause license contributed to the NetBSD Foundation to a 2-clause license." This change removes clauses 3 and 4 from copyright / license blocks that list The NetBSD Foundation as the only copyright holder. Sponsored by: The FreeBSD Foundation
* Update MIPS bootinfo.h to reflect the actual MIPS boot2/loader boot-timerwatson2014-02-191-87/+30
| | | | | | | interface. MFC after: 3 weeks Sponsored by: DARPA, AFRL
* Retire machine/fdt.h as a header used by MI code, as its function is nownwhitehorn2014-01-051-11/+0
| | | | | | | | | | | | | | | obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
* As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In otheralc2013-11-081-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | words, every architecture is now auto-sizing the kmem arena. This revision changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and the definition of VM_KMEM_SIZE becomes optional. Replace or eliminate all existing definitions of VM_KMEM_SIZE. With auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for clarity. Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to that of setting the tunable vm.kmem_size. Whereas the macros VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set the size of the kmem arena at compile-time without that value being overridden by auto-sizing. Update the nearby comments to reflect the kmem submap being replaced by the kmem arena. Stop duplicating the auto-sizing formula in every machine- dependent vmparam.h and place it in kmeminit() where auto-sizing takes place. Reviewed by: kib (an earlier version) Sponsored by: EMC / Isilon Storage Division
* MFP4:brooks2013-10-231-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30 FreeBSD/mips stores page-table entries in a near-identical format to MIPS TLB entries -- only it overrides certain "reserved" bits in the MIPS-defined EntryLo register to hold software-defined bits (swbits) to avoid significantly increasing the page table memory footprint. On n32 and n64, these bits were (a) colliding with MIPS64r2 physical memory extensions and (b) being improperly cleared. Attempt to fix both of these problems by pushing swbits further along 64-bit EntryLo registers into the reserved space, and improving consistency between C-based and assembly-based clearing of swbits -- in particular, to use the same definition. This should stop swbits from leaking into TLB entries -- while ignored by most current MIPS hardware, this would cause a problem with (much) larger physical memory sizes, and also leads to confusing hardware-level tracing as physical addresses contain unexpected (and inconsistent) higher bits. Discussed with: imp, jmallett Change 1187301 by brooks@brooks_zenith on 2013/10/23 14:40:10 Loop back the initial commit of 221534 to HEAD. Correct its implementation for mips32. MFC after: 3 days Sponsored by: DARPA/AFRL
* Revert r256934, it needs work to build on mips32.brooks2013-10-231-22/+9
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* MFP4:brooks2013-10-221-1/+6
| | | | | | | | | | Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30 Add kernel side support for large TLB on BERI/CHERI. Modelled similar to NLM MFC after: 3 days Sponsored by: DAPRA/AFRL
* MFP4:brooks2013-10-221-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30 FreeBSD/mips stores page-table entries in a near-identical format to MIPS TLB entries -- only it overrides certain "reserved" bits in the MIPS-defined EntryLo register to hold software-defined bits (swbits) to avoid significantly increasing the page table memory footprint. On n32 and n64, these bits were (a) colliding with MIPS64r2 physical memory extensions and (b) being improperly cleared. Attempt to fix both of these problems by pushing swbits further along 64-bit EntryLo registers into the reserved space, and improving consistency between C-based and assembly-based clearing of swbits -- in particular, to use the same definition. This should stop swbits from leaking into TLB entries -- while ignored by most current MIPS hardware, this would cause a problem with (much) larger physical memory sizes, and also leads to confusing hardware-level tracing as physical addresses contain unexpected (and inconsistent) higher bits. Discussed with: imp, jmallett MFC after: 3 days Sponsored by: DARPA/AFRL
* Elminate NON_LEAF and use NESTED instead to unify our assemblerimp2013-10-151-6/+0
| | | | | | conventions. Reviewed by: jmallet@
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