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* MFC r294463:brooks2016-01-281-14/+15
| | | | | | | | | Shift saved floating point registers up in jmp_buf. sigmask_t is 128-bits so requires two slots. Obtained from: CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc) Sponsored by: DARPA, AFRL
* MFC r276539: Update ELF headers to include additional definesemaste2016-01-201-29/+0
| | | | | | | | | | | | The elftoolchain project includes these additional defines for various userland programs. Given that arch-specific defines are still interesting in the context of userland programs reading or writing ELF metadata, they should be included in top-level ELF headers. Remove duplicate defines from ARM and MIPS elf headers. Submitted by: will (initial version) Sponsored by: The FreeBSD Foundation
* MFC 283645:jhb2015-10-271-0/+1
| | | | | Similarly to other architecture, add the include for cpufunc.h which is needed for pte.h by vmstat to resolve MIPS_CCA_UNCACHED.
* MFC r276439 (by alc):kib2015-07-161-11/+9
| | | | | | | | | | | Make the creation of the free lists dynamic, i.e., it is based on the available physical memory at boot time. For amd64 systems with 64 GB or more of physical memory, create free lists for managing pages with physical addresses below 4 GB. PR: 185727 Requested by: alc Approved by: re (gjb)
* MFC r269137 by marcel:emaste2015-07-021-0/+2
| | | | | | Add missing definition of ELF_MACHINE_OK, now used by gcore(1). PR: 201204
* MFC 281266:jhb2015-06-021-1/+3
| | | | | | | | | | | | Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h> and export them to userland. - Define __HAVE_REG32 on platforms that define a reg32 structure and check for this in <sys/procfs.h> to control when to export prstatus32, etc. - Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures. libbfd looks for these types, and having them fixes 'gcore' in gdb of a 32-bit process on a 64-bit platform. - Use the structure definitions from <sys/procfs.h> in gcore's elf32 core dump code instead of duplicating the definitions.
* MFC r274816:brooks2015-01-221-0/+14
| | | | | | | | | | | | | | Add FPU support for MIPS setjmp(3)/longjmp(3). This change saves/restores the callee-saved MIPS floating point registers as documented by the o32/n32/n64 spec ("MIPSpro N32 ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3), setjmp(3) and longjmp(3) C library functions. This is only included when the C library is built with hardware floating point support (or when "SOFTFLOAT" is not defined). Submitted by: sson Sponsored by: DARPA, AFRL
* Merge the fueword(9) and casueword(9). In particular,kib2014-11-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | MFC r273783: Add fueword(9) and casueword(9) functions. MFC note: ia64 is handled like arm, with NO_FUEWORD define. MFC r273784: Replace some calls to fuword() by fueword() with proper error checking. MFC r273785: Convert kern_umtx.c to use fueword() and casueword(). MFC note: the sys__umtx_lock and sys__umtx_unlock syscalls are not converted, they are removed from HEAD, and not used. The do_sem2*() family is not yet merged to stable/10, corresponding chunk will be merged after do_sem2* are committed. MFC r273788 (by jkim): Actually install casuword(9) to fix build. MFC r273911: Add type qualifier volatile to the base (userspace) address argument of fuword(9) and suword(9).
* MFC r257854 (discussed with alc@)ian2014-05-161-9/+10
| | | | | | | | | | | | | As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other words, every architecture is now auto-sizing the kmem arena. This revision changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and the definition of VM_KMEM_SIZE becomes optional. Replace or eliminate all existing definitions of VM_KMEM_SIZE. With auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for clarity.
* MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,ian2014-05-141-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373, r260374, r260375 Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs. Correct license statements to reflect the fact that these files were all derived from sys/arm/mv/bus_space.c. In pmap_unmapdev(), remember the size, and use that as an argument to kva_free(), or we'd end up always passing it a size of 0 In pmap_mapdev(), first check whether a static mapping exists, Convert TI static device mapping to use the new arm_devmap_add_entry(), Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy. Eliminate use of fdt_immr_addr(), it's not needed for tegra Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make static device mappings. Retire machine/fdt.h as a header used by MI code, as its function is now obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed. Add #include <machine/fdt.h> to a few files that used to get it via pollution Enable the mv cesa security/crypto device by providing the required property in the dts source, and adding the right devices to the kernel config. Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs, related to setting up static device mappings. Since it was only used by arm/mv/mv_pci.c, it's now just static functions within that file, plus one public function that gets called only from arm/mv/mv_machdep.c. Switch RPi to using arm_devmap_add_entry() to set up static device mapping. Allow 'no static device mappings' to potentially work. Don't try to find a static mapping before calling pmap_mapdev(), that logic is now part of pmap_mapdev() and doesn't need to be duplicated here. Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
* MFC r263998:tijl2014-04-151-1/+1
| | | | | Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4 -fms-extensions.
* MFC r263289: Update NetBSD Foundation copyrights to 2-clause BSDemaste2014-03-241-7/+0
| | | | | | | | | | | The NetBSD Foundation states "Third parties are encouraged to change the license on any files which have a 4-clause license contributed to the NetBSD Foundation to a 2-clause license." This change removes clauses 3 and 4 from copyright / license blocks that list The NetBSD Foundation as the only copyright holder. Sponsored by: The FreeBSD Foundation
* MFC r256935brooks2013-11-011-1/+6
| | | | | | | | | | | MFP4: Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30 Add kernel side support for large TLB on BERI/CHERI. Modelled similar to NLM Sponsored by: DAPRA/AFRL Approved by: re (delphij)
* MFC r256934, r256963, r256972, r257017brooks2013-11-011-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MFP4: Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30 FreeBSD/mips stores page-table entries in a near-identical format to MIPS TLB entries -- only it overrides certain "reserved" bits in the MIPS-defined EntryLo register to hold software-defined bits (swbits) to avoid significantly increasing the page table memory footprint. On n32 and n64, these bits were (a) colliding with MIPS64r2 physical memory extensions and (b) being improperly cleared. Attempt to fix both of these problems by pushing swbits further along 64-bit EntryLo registers into the reserved space, and improving consistency between C-based and assembly-based clearing of swbits -- in particular, to use the same definition. This should stop swbits from leaking into TLB entries -- while ignored by most current MIPS hardware, this would cause a problem with (much) larger physical memory sizes, and also leads to confusing hardware-level tracing as physical addresses contain unexpected (and inconsistent) higher bits. Discussed with: imp, jmallett Change 1187301 by brooks@brooks_zenith on 2013/10/23 14:40:10 Loop back the initial commit of 221534 to HEAD. Correct its implementation for mips32. Sponsored by: DARPA/AFRL Approved by: re (gjb)
* Add "better" MIPS24k and MIPS74k barriers.adrian2013-10-092-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * the mips74k cores only need EHB (which is 'sll $0, $0, 3') here; NOPs don't actually work. * add EHB as the last NOP for the default barriers/hazards; that is "better" behaviour and should work on a wider variety of processors. This allows the existing (icky) TLB code to work, allowing the AR9344 SoC (mips74k) to actually get through kernel startup. Tested: * AR9344 SoC - (mips74k) * AR9331 SoC - (mips24k) TODO: * test on mips4k CPUs, just to be sure. * document that sll $0, $0, 3 is actually "EHB" and that it falls back to being a NOP for pre-mips32r1. * mips24k has an errata that we currently don't correctly explicitly state - ie, that after DERET/ERET, the only valid instruction is a NOP. Reviewed by: imp@ Approved by: re@ (gjb)
* Fix build with gcc. Move sf_buf_alloc()/sf_buf_free() declarationsglebius2013-09-061-0/+3
| | | | to MD headers.
* On those machines, where sf_bufs do not represent any real object, makeglebius2013-09-061-0/+12
| | | | | | | | | sf_buf_alloc()/sf_buf_free() inlines, to save two calls to an absolutely empty functions. Reviewed by: alc, kib, scottl Sponsored by: Nginx, Inc. Sponsored by: Netflix
* Newer versions of gcc define __INT64_C and __UINT64_C, so avoidimp2013-09-031-0/+2
| | | | redefining them if gcc provides them.
* Revert r253748,253749avg2013-07-281-3/+2
| | | | | | This WIP should not have been committed yet. Pointyhat to: avg
* put contents of cpu.h under _KERNELavg2013-07-281-2/+3
| | | | | | no userland-serviceable parts inside MFC after: 20 days
* Nearly a complete rewrite of elf.h.imp2013-07-091-187/+182
| | | | | | | | | | | | | | | | | | | | | | Start with NetBSD's sys/arch/mips/include/elf_machdep.h 1.18. Remove the NetBSD specific glue pieces (leaving mostly just relocation types). Add in FreeBSD specific glue pieces from older versions of this file, and move to the top of the file: r237430 | kib | 2012-06-22 00:38:31 -0600 (Fri, 22 Jun 2012) | 5 lines r232449 | jmallett | 2012-03-03 01:19:18 -0700 (Sat, 03 Mar 2012) | 18 lines r217097 | kib | 2011-01-07 07:22:34 -0700 (Fri, 07 Jan 2011) | 3 lines r211412 | kib | 2010-08-17 02:55:45 -0600 (Tue, 17 Aug 2010) | 7 lines r202908 | gonzo | 2010-01-23 19:59:22 -0700 (Sat, 23 Jan 2010) | 4 lines r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines r197933 | kib | 2009-10-10 09:31:24 -0600 (Sat, 10 Oct 2009) | 9 lines r189926 | kib | 2009-03-17 06:50:16 -0600 (Tue, 17 Mar 2009) | 9 lines r186191 | imp | 2008-12-16 13:07:47 -0700 (Tue, 16 Dec 2008) | 7 lines as closely as I can tell, the projects/mips branch merge was disruptive to good history. This should make merges easier in the future from NetBSD and vice versa.
* Remove all the NOPs after SYNC. They aren't needed.imp2013-07-071-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They originated in the original Octeon port. They weren't present, as far as I can tell, on the projects/mips branch until after this point. They were in the original Octeon port in code picked up from the vendor, who I've been able to find out trolling old email put them there to get around an SMP problem that most likely was fixed in other ways. NetBSD and Linux don't have these, except for some specific uses of SYNC on the alchemy parts (which we don't support, but even if we did it is only a specific case and would be specifically coded anyway). This is true of the current Linux code, as well as one old version I polled. I looked back at the old R12000, R8000, R6000, R4000, R4400 errata that I have, and could find no mention of SYNC needing NOPs for silicon bugs (although plenty of other cases where NOPs and other contortions were needed). An Google search turned up no old mailing list discussions on this on Linux, NetBSD or FreeBSD (except the disussion that kicked off these studies). I've test booted this on my Octeon Plus eval board and survived a buildworld. Adrian Chadd reports that this patch has no ill effects on the Ahteros platforms he tested it on. I conclude it is safe to just remove the NOPs. But added __MIPS_PLATFORM_SYNC_NOPS as a failsafe in case we find some platform where these are, in fact, required. Reviewed by: adrian@
* Fix issues with zeroing and fetching the counters, on x86 and ppc64.kib2013-07-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues were noted by Bruce Evans and are present on all architectures. On i386, a counter fetch should use atomic read of 64bit value, otherwise carry from the increment on other CPU could be lost for the given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not available on the machine, it cannot be SMP and it is enough to disable preemption around read to avoid the split read. On x86 the counter increment is not atomic on purpose, which makes it possible for the store of the incremented result to override just zeroed per-cpu slot. The effect would be a counter going off by arbitrary value after zeroing. Perform the counter zeroing on the same processor which does the increments, making the operations mutually exclusive. On i386, same as for the fetching, if the cmpxchg8b is not available, machine is not SMP and we disable preemption for zeroing. PowerPC64 is treated the same as amd64. For other architectures, the changes made to allow the compilation to succeed, without fixing the issues with zeroing or fetching. It should be possible to handle them by using the 64bit loads and stores atomic WRT preemption (assuming the architectures also converted from using critical sections to proper asm). If architecture does not provide the facility, using global (spin) mutex would be non-optimal but working solution. Noted by: bde Sponsored by: The FreeBSD Foundation
* Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h inattilio2013-05-072-7/+4
| | | | | | | | | order to match the MAXCPU concept. The change should also be useful for consolidation and consistency. Sponsored by: EMC / Isilon storage division Obtained from: jeff Reviewed by: alc
* Don't include asm.h in non-asm files.imp2013-05-012-115/+0
| | | | | | Remove #define to get kludges that asm.h used to define Move clever macros to access assembler instructions to trap.c Remove __ASSEMBLER__ ifdefs in regdef.h: they aren't needed anymore.
* Import NetBSD's version, which is perfectly fine.imp2013-05-011-38/+76
| | | | Submitted by: jmallet@
* Add the standard #ifdef header protection.imp2013-05-011-0/+5
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* Import virgin regdef.h from 4.4 Lite 2's sys/pmax/include/regdef.h,imp2013-05-011-81/+62
| | | | | | | expand the %sccs.include.redist.c% directive with the standard 3-clause license, and add $FreeBSD$ to keep the commit script happy. # This may break some mips stuff, which will be fixed in the next commit.
* Use the offsets from pcb.h rather than regnum.h to store the registersimp2013-04-251-18/+0
| | | | | | | | | in the pcb. setjmp/longjmp in the kernel also used these values, so continue to use them although their use isn't technically the pcb register array (matching is all that's important for setjmp/longjmp in the kernel). Finally, eliminate the old register names from regnum.h. This is a lexical change only. The non-debug .o files have the same md5.
* Make it possible to include this file in assembler .S sources.imp2013-04-251-13/+14
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* Update trapframe to be consistent with the changes made to regnum.h. Thisimp2013-04-232-4/+17
| | | | should fix the booting problems people have been seeing.
* MFP4 223084, 227821:brooks2013-04-221-0/+6
| | | | | | | | | | | | Partially implement generic_bs_*_8() for MIPS platforms. This is known to work with TARGET_ARCH=mips64 with FreeBSD/BERI. Assuming that other definitions in cpufunc.h are correct it will work on non-o64 ABI systems except sibyte. On sibyte and o32 systems generic_bs_*_8() will remain panic() implementations. Sponsored by: DARPA, AFRL Reviewed by: imp, jmallett (older versions)
* Point to regdef.h. May need to dig up references to the N32 standardimp2013-04-161-1/+1
| | | | | that support this usage (which may be a bit rough, since different parts of the standard say mutually contradictory things).
* Fix N32/N64 register saving by ensuring that all registers resolveimp2013-04-151-3/+31
| | | | | | | | | | | | | | to unique values. There's some confusion about what the n32 assembler API really is (since on page 9 of the spec they say that t0-t3 don't exist, then turn around on page 22 and say that t4-t7 don't exist), and this doesn't touch that. NetBSD's version of this file follows the convention I used here, and is likely to be correct. This should fix gdb/ptrace.
* Move MIPS_MAX_TLB_ENTRIES definition from cpuregs.h to tlb.cjchandra2013-04-121-1/+0
| | | | | | | | | | | | | | | Having MIPS_MAX_TLB_ENTRIES defined to 128 is misleading, since it used to be 64 in older releases of MIPS architecture (where it could be read from Config1) and can be much more than 128 for the newer processors. For now, move the definition to the only file using it (mips/mips/tlb.c) and define MIPS_MAX_TLB_ENTRIES depending on the MIPS cpu defined. Also add few checks so that we do not write beyond the end of the tlb_state array. This fixes a kernel data corruption seen in Netlogic XLP, which was casued by tlb_save() writing beyond the end of tlb_state array when breaking into debugger.
* Merge from projects/counters: counter(9).glebius2013-04-081-0/+54
| | | | | | | | | | | | | Introduce counter(9) API, that implements fast and raceless counters, provided (but not limited to) for gathering of statistical data. See http://lists.freebsd.org/pipermail/freebsd-arch/2013-April/014204.html for more details. In collaboration with: kib Reviewed by: luigi Tested by: ae, ray Sponsored by: Nginx, Inc.
* Merge from projects/counters:glebius2013-04-081-1/+17
| | | | | | | Pad struct pcpu so that its size is denominator of PAGE_SIZE. This is done to reduce memory waste in UMA_PCPU_ZONE zones. Sponsored by: Nginx, Inc.
* Define VM_KMEM_SIZE_MAX as a fraction of the kernel address space sizealc2013-01-121-2/+3
| | | | | | | | rather than a constant so that VM_KMEM_SIZE_MAX will scale automatically with the kernel address space size. This is particularly important for MIPS because the same definition is used by both 32- and 64-bit kernels. Tested by: jchandra
* Merge Perforce changeset 219925 to head:rwatson2013-01-122-1/+3
| | | | | | | | | | | Provided a bus_space implementation for FDT, modelled on bus_space_generic, but with a local version of the map address routine that does a P->V translation, as is the case with NLM's similar routine for XLP. It's not clear to me that this is the right solution -- possibly this belongs in simplebus -- however, it is sufficient to get the DE4 LED driver working. Sponsored by: DARPA, AFRL
* Merge Perforce change @219948 to head:rwatson2013-01-121-0/+1
| | | | | | | | | | Add code so that the BERI boot process can ask the kernel linker for DTB blobs that may have been left for it by the boot loader, as done on PowerPC and ARM. This will require both a more mature boot loader, and more mature boot loader argument passing mechanism, than currently supported on BERI. Sponsored by: DARPA, AFRL
* Eliminate some definitions that haven't been used in a decade or more.alc2012-12-191-14/+0
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* The function pmap_alloc_direct_page() unconditionally zeroes the returnedalc2012-11-141-1/+0
| | | | | | page. Therefore, it is really inappropriate for use by the function uma_small_alloc(). The effect of using it was that every page was zeroed at least once and possibly twice if M_ZERO was passed as a "wait" flag.
* Add an unified macro to deny ability from the compiler to reorderattilio2012-10-091-1/+1
| | | | | | | | | | instruction loads/stores at its will. The macro __compiler_membar() is currently supported for both gcc and clang, but kernel compilation will fail otherwise. Reviewed by: bde, kib Discussed with: dim, theraven MFC after: 2 weeks
* Introduce a new TLB invalidation function for efficiently invalidatingalc2012-10-021-0/+1
| | | | | | address ranges, and use this function in pmap_remove(). Tested by: jchandra
* Introduce a new software PTE flag that indicates whether the mapping isalc2012-09-012-7/+8
| | | | | | for a managed page. Tested by: jchandra
* Add MD syscons header file for MIPS.rwatson2012-08-251-0/+71
| | | | Sponsored by: DARPA, AFRL
* Retire PV_TABLE_MOD. When we destroy or write protect a dirty mapping,alc2012-08-251-1/+0
| | | | | we call vm_page_dirty(). Maintaining the PV_TABLE_MOD flag, in addition, serves no useful purpose.
* Port the new PV entry allocator from amd64/i386. This allocator has twoalc2012-08-131-5/+21
| | | | | | | | | | | | | advantages. First, PV entries are roughly half the size. Second, this allocator doesn't access the paging queues, and thus it will allow for the removal of the page queues lock from this pmap. Fix a rather serious bug in pmap_remove_write(). After removing write access from the specified page's first mapping, pmap_remove_write() then used the wrong "next" pointer. Consequently, the page's second, third, etc. mappings were not write protected. Tested by: jchandra
* Merge r132141 and r111272 from amd64/i386:alc2012-08-091-2/+0
| | | | | | | | | | | | | Reduce the size of a PV entry by eliminating pv_ptem. There is no need to store a pointer to the page table page in the PV entry because it is easily computed during the walk down the page table. Eliminate the ptphint from the pmap. Long, long ago, page table pages belonged to a vm object, and we would look up page table pages based upon their offset within this vm object. In those days, this hint may have had tangible benefits. Tested by: jchandra
* Make the wchar_t type machine dependent.andrew2012-06-242-6/+4
| | | | | | | | | | | | | | This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an unsigned short with the former preferred. Because of this requirement we need to move the definition of __wchar_t to a machine dependent header. It also cleans up the macros defining the limits of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine dependent header then using them to define WCHAR_MIN and WCHAR_MAX respectively. Discussed with: bde
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