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* Implement mechanism to export some kernel timekeeping data tokib2012-06-221-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usermode, using shared page. The structures and functions have vdso prefix, to indicate the intended location of the code in some future. The versioned per-algorithm data is exported in the format of struct vdso_timehands, which mostly repeats the content of in-kernel struct timehands. Usermode reading of the structure can be lockless. Compatibility export for 32bit processes on 64bit host is also provided. Kernel also provides usermode with indication about currently used timecounter, so that libc can fall back to syscall if configured timecounter is unknown to usermode code. The shared data updates are initiated both from the tc_windup(), where a fast task is queued to do the update, and from sysctl handlers which change timecounter. A manual override switch kern.timecounter.fast_gettime allows to turn off the mechanism. Only x86 architectures export the real algorithm data, and there, only for tsc timecounter. HPET counters page could be exported as well, but I prefer to not further glue the kernel and libc ABI there until proper vdso-based solution is developed. Minimal stubs neccessary for non-x86 architectures to still compile are provided. Discussed with: bde Reviewed by: jhb Tested by: flo MFC after: 1 month
* Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer tokib2012-06-221-0/+1
| | | | | | timekeeping information. MFC after: 1 week
* The page flag PGA_WRITEABLE is set and cleared exclusively by the pmapalc2012-06-161-0/+1
| | | | | | | | | | | | | | | | layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks
* MFp4 bz_ipv6_fast:bz2012-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | in_cksum.h required ip.h to be included for struct ip. To be able to use some general checksum functions like in_addword() in a non-IPv4 context, limit the (also exported to user space) IPv4 specific functions to the times, when the ip.h header is present and IPVERSION is defined (to 4). We should consider more general checksum (updating) functions to also allow easier incremental checksum updates in the L3/4 stack and firewalls, as well as ponder further requirements by certain NIC drivers needing slightly different pseudo values in offloading cases. Thinking in terms of a better "library". Sponsored by: The FreeBSD Foundation Sponsored by: iXsystems Reviewed by: gnn (as part of the whole) MFC After: 3 days
* Add a convenience macro for the returns_twice attribute, and apply it todim2012-04-291-1/+1
| | | | | | | the prototypes of the appropriate functions (getcontext, savectx, setjmp, sigsetjmp and vfork). MFC after: 2 weeks
* Use VM_MEMATTR_UNCACHEABLE for the constant for UC memory rather thanjhb2012-03-291-1/+1
| | | | | | | VM_MEMATTR_UNCACHED. VM_MEMATTR_UNCACHEABLE is the constant other platforms use. MFC after: 2 weeks
* Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.jmallett2012-03-291-4/+4
| | | | | | | | | | | | | | | This makes our naming scheme more closely match other systems and the expectations of much third-party software. MIPS builds which are little-endian should require and exhibit no changes. Big-endian TARGET_ARCHes must be changed: From: To: mipseb mips mipsn32eb mipsn32 mips64eb mips64 An entry has been added to UPDATING and some foot-shooting protection (complete with warnings which should become errors in the near future) to the top-level base system Makefile.
* Add software PMC support.fabient2012-03-281-1/+1
| | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
* Fix pmap_kextract prototype to align it with pmap.c changegonzo2012-03-231-1/+1
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* Rework MIPS PMC code:gonzo2012-03-221-7/+49
| | | | | | | | - Replace MIPS24K-specific code with more generic framework that will make adding new CPU support easier - Add MIPS24K support for new framework - Limit backtrace depth to 1 for stability reasons and add option HWPMC_MIPS_BACKTRACE to override this limitation
* o) Use ABI, not ISA_* options, to determine whether to compile bits if libkernjmallett2012-03-121-1/+1
| | | | | | | required for the ABI the kernel is being built for. XXX This is implemented in a kind-of nasty way that involves including source files, but it's still an improvement. o) Retire ISA_* options since they're unused and were always wrong.
* Use 64-bit bus space constants on 64-bit kernels.jmallett2012-03-121-3/+11
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* Remove more unused stuff, primarily a set of (unused, thankfully) PIOjmallett2012-03-121-112/+2
| | | | | | functions. Adjust nearby style of one assembly function END().
* Remove more unused code and declarations, and add dire warnings to the 64-bitjmallett2012-03-126-17/+0
| | | | atomic ops used by 32-bit kernels.
* Remove platform APIs which are not used by any code and which had only stubjmallett2012-03-123-16/+3
| | | | | | | | | implementations or no implementation on all platforms. Some of these functions might be good ideas, but their semantics were unclear given the lack of implementation, and an unlucky porter could be fooled into trying to implement them or, worse, being baffled when something like platform_trap_enter() failed to be called.
* Remove some headers not used by kernel or world and which are not present injmallett2012-03-108-329/+0
| | | | other ports.
* Fix reversed logic in previous commit that broke build and earned me quite thejmallett2012-03-101-2/+2
| | | | | | pointy hat. Submitted by: bz
* Use ABI to determine bus_addr_t for cnMIPS.jmallett2012-03-101-1/+1
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* Get rid of duplicated versions of the KSU bits.jmallett2012-03-061-6/+1
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* At the risk of reducing source compatibility with old NetBSD and Sprite:jmallett2012-03-063-459/+61
| | | | | | | | | | | | | | | | | | | | | o) Get rid of some unused macros related to features we don't intend to provide. o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to support anything that predartes MIPS-III. o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being used already. o) Eliminate a duplicate and mostly-unused set of exception vector macros. There's still considerable duplication and lots more obsolete in our headers, but this reduces one of the larger files to a size where one could reckon about the correctness of its contents with a mere few hours of contemplation. There is, of course, a question of whether we need definitions for fields, registers and configurations that we are unlikely to ever use or implement, even if they're not obsolete since 1991. FreeBSD is not a processor reference manual, and things that aren't used may be wrong, or may be duplicated because nobody could possibly actually know whether they're already defined.
* Fix two and a half oversights in COMPAT_FREEBSD32 related to contexts andjmallett2012-03-061-1/+1
| | | | | | | | | | | | | TLS: o) The mc_tls field used to store the TLS base when doing context gets and restores was left a pointer and not converted to a 32-bit integer. This had the bug of not correctly capturing the TLS value desired by the user, and the extra nastiness of making the structure the wrong size. o) The mc_tls field was not being saved by sendsig. As a result, the TLS base would always be set to NULL when restoring from a signal handler. Thanks to gonzo for helping track down a bunch of other TLS bugs that came out of tracking these down.
* When emulating rdhwr for TLS, use the 32-bit offset under COMPAT_FREEBSD32.jmallett2012-03-061-0/+7
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* Prepare for large TLS redo. Save pointer to the beginning of TLS area,gonzo2012-03-061-0/+48
| | | | | | and offset it only if requested by RDHWR handler. Otherwise things get overly complicated - we need to track whether address passsed in request for setting td_md.md_tls is already offseted or not.
* o) Add COMPAT_FREEBSD32 support for MIPS kernels using the n64 ABI with ↵jmallett2012-03-038-2/+98
| | | | | | | | | | | | | | | | | | | | | userlands using the o32 ABI. This mostly follows nwhitehorn's lead in implementing COMPAT_FREEBSD32 on powerpc64. o) Add a new type to the freebsd32 compat layer, time32_t, which is time_t in the 32-bit ABI being used. Since the MIPS port is relatively-new, even the 32-bit ABIs use a 64-bit time_t. o) Because time{spec,val}32 has the same size and layout as time{spec,val} on MIPS with 32-bit compatibility, then, disable some code which assumes otherwise wrongly when built for MIPS. A more general macro to check in this case would seem like a good idea eventually. If someone adds support for using n32 userland with n64 kernels on MIPS, then they will have to add a variety of flags related to each piece of the ABI that can vary. That's probably the right time to generalize further. o) Add MIPS to the list of architectures which use PAD64_REQUIRED in the freebsd32 compat code. Probably this should be generalized at some point. Reviewed by: gonzo
* - Fix spelling of R_MIPS_RELGOTgonzo2012-02-101-2/+20
| | | | | | | - Add R_MIPS_JALR relocation - Add TLS relocation types Obtained from: NetBSD
* - Emulate RDHWR instruction for TLS supportgonzo2012-02-091-0/+10
| | | | | | | | | | | Reading register $29 with RDHWR is becoming the de-facto standard to implement TLS. According to linux-mips wiki, MIPS Technologies has reserved hardware register $29 for ABI use. Furthermore current GCC makes the following assumptions: - RDHWR is natively available or otherwise emulated by the kernel - Register $29 holds the TLS pointer Submitted by: Robert Millan <rmh@debian.org>
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+15
| | | | Reviewed by: bde
* Add parentheses where required. Without them, `sizeof LDBL_MAX'das2012-01-201-4/+4
| | | | | is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a syntax error and should be. Thanks to bde for the examples.
* Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.das2012-01-161-1/+1
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* Remove a confused comment and fix some minor bugs.das2012-01-161-7/+6
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* Fix backtrace for MIPS64:gonzo2012-01-131-1/+2
| | | | | | - Properly print 64-bit addresses - Get whole 64 bits of address using kdbpeekd - Make check for kernel address compatible with MIPS64
* - Add better COP2 (crypto coprocessor) context handler for Octeon. Keepgonzo2012-01-064-5/+228
| | | | | COP2 disabled and lazily allocate COP2 context structure in exception handler. Keep kernel and userland contexts separated.
* Apply the same change as in r229494.andreast2012-01-041-3/+11
| | | | Requested by: ed
* Remove trailing white-space.marcel2011-12-301-4/+4
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* Replace __signed by signed.ed2011-12-131-1/+1
| | | | | The signed keyword is an integral part of the C syntax. There's no need to use __signed.
* XLP processors have the release 2 pagegrain registerjchandra2011-11-211-0/+3
| | | | | | Add accessors to cpufunc.h Obtained from: prabhath at netlogicmicro com
* Fix COP0 hazards for XLR and XLPjchandra2011-11-183-1/+12
| | | | | The XLR CPUs do not have any software visible hazards for COP0 operations. On XLP the hazard is a ehb, since it is mips64r2.
* People porting FreeBSD to new architectures ought not have todas2011-10-211-0/+2
| | | | | | | | | | | | | implement a deprecated FPU control interface in addition to the standard one. To make this clearer, further deprecate ieeefp.h by not declaring the function prototypes except on architectures that implement them already. Currently i386 and amd64 implement the ieeefp.h interface for compatibility, and for fp[gs]etprec(), which doesn't exist on most other hardware. Powerpc, sparc64, and ia64 partially implement it and probably shouldn't, and other architectures don't implement it at all.
* Fix wakeup latency when sleeping with 'wait'jchandra2011-10-181-0/+1
| | | | | | | | | | | | | | | | | If we handle an interrupt just before the 'wait' and the interrupt schedules some work, we need to skip the 'wait' call. The simple solution of calling sched_runnable() with interrupts disabled immediately before wait still leaves a window after the call and before 'wait' in which the same issue can occur. The solution implemented is to check the EPC in the interrupt handler, and if it is in a region before the 'wait' call, to fix up the EPC to skip the wait call. Reported/analysed by: adrian Fix suggested by: kib Reviewed by: jmallett, imp
* Support for booting XLP using FDT.jchandra2011-10-182-0/+5
| | | | | | | | - update xlp_machdep.c to read arguments from FDT if FDT support is compiled in. - define rmi_uart_bus_space, and use it as fdtbus_bs_tag - update conf files for FDT support - add default dts file xlp-basic.dts
* FDT support for MIPS.jchandra2011-10-183-0/+103
| | | | | Add architecture specific files needed to compile MIPS with flattened device tree support.
* Remove unused define.kib2011-10-071-1/+0
| | | | MFC after: 1 month
* Convert MIPS to the syscallenter/syscallret system call sequence handlers.kib2011-10-061-0/+11
| | | | | | | This was the last architecture used custom syscall entry sequence. Reviewed, debugged, tested and approved by: jchandra MFC after: 1 month
* Remove bogus and wrong definition of BLKDEV_IOSIZE.marcel2011-10-041-1/+0
| | | | | | Wrong in that it must be guarded (it's configurable) and bogus in that there's absolutely no rationale for it not default to a page size like all other archs.
* Add the possibility to specify from kernel configs MAXCPU value.attilio2011-07-191-0/+2
| | | | | | | | | | This patch is going to help in cases like mips flavours where you want a more granular support on MAXCPU. No MFC is previewed for this patch. Tested by: pluknet Approved by: re (kib)
* MIPS changes for Netlogic XLP support.jchandra2011-07-163-2/+6
| | | | | | | | | | | | | | This patch adds support for the Netlogic XLP mips64 processors in the common MIPS code. The changes are : - Add CPU_NLM processor type - Add cases for CPU_NLM, mostly were CPU_RMI is used. - Update cache flush changes for CPU_NLM - Add kernel build configuration files for xLP. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
* MFCattilio2011-05-131-0/+2
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* Fix a brain-o in platform_cpu_mask() by just specifying a possibleattilio2011-05-131-1/+1
| | | | | | | cpuset_t to be copied, rather than return the array. I can't rely anymore on this being a simple int/long object. Reported by: art
* Add the cpuset_t conversion for mips.attilio2011-05-134-4/+8
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* Fix the _long() rappresentation on mips by casting the long argumentsattilio2011-05-131-23/+38
| | | | | | to u_int for all the functions. Reviewed by: art, imp
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