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* - Remove <machine/mutex.h>. Most of the headers were empty, and thejhb2010-11-091-2/+0
* - Add minidump support for FreeBSD/mipsgonzo2010-11-073-0/+10
* Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.neel2010-09-221-0/+1
* Get rid of the unnecessary redirection of 'is_cacheable_mem()' toneel2010-09-171-3/+1
* Get rid of unused macros.neel2010-09-171-29/+0
* Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistentneel2010-09-151-1/+1
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+0
* The functions in sys/mips/mips/psraccess.S can be implemented withjchandra2010-09-132-5/+19
* Remove misleading comment in pte.h. MIPS PTE entries are software managedjchandra2010-08-301-3/+0
* Apply MIPS pmap clean up patch from alc@ (with minor change to KASSERT):jchandra2010-08-291-5/+0
* Whitespace fixes in mips/include, remove unused 'struct tlb' from locore.hjchandra2010-08-276-51/+49
* MIPS n64 support - continued...jchandra2010-08-182-11/+25
* Supply some useful information to the started image using ELF aux vectors.kib2010-08-171-1/+7
* Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.jchandra2010-08-132-2/+2
* Implement pmap changes suggested by alc@:jchandra2010-08-121-3/+1
* Update various places that store or manipulate CPU masks to use cpumask_tjhb2010-08-111-1/+1
* Add parentheses around the argument 'x' used in the __bswapXX(x) macros. Revertneel2010-08-111-6/+6
* - Consolidate the the cache coherence attribute definitions in a single place.neel2010-08-072-15/+66
* Add a new ipi_cpu() function to the MI IPI API that can be used to send anjhb2010-08-061-0/+1
* Fix the issue reported by alc:jchandra2010-08-061-1/+0
* Add 3 level page tables for MIPS in n64.jchandra2010-08-042-2/+12
* Prepare for 3 level page tables for MIPS.jchandra2010-07-292-17/+15
* Update MIPS _stdint.h for 64 bit. Initial 64 bit changes for profile.h.jchandra2010-07-292-4/+40
* Fix RQB_FFS for 64 bit, we need to use ffsl() for 64bit.jchandra2010-07-291-2/+6
* Very rough first cut at NUMA support for the physical page allocator. Forjhb2010-07-271-0/+7
* Get N64 building by defining VM_FREELIST_DIRECT to beimp2010-07-251-0/+1
* Update MIPS timer code (except RMI) to utilize new MI event timermav2010-07-231-0/+3
* Redo the page table page allocation on MIPS, as suggested byjchandra2010-07-211-4/+14
* Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executivejmallett2010-07-204-4/+4
* Move common macros into asm.h. Replace MIPS_CPU_NOP_DELAY withimp2010-07-161-0/+14
* This file appears not to be used.imp2010-07-161-198/+0
* Use #define for get_cyclecount rather than inline function.imp2010-07-161-5/+1
* Better description of this fileimp2010-07-151-1/+4
* Move TLB definitions to tlb.himp2010-07-152-19/+20
* This file has been unused for a while now...imp2010-07-151-46/+0
* Remove unused stuff from cpu.h.imp2010-07-154-149/+12
* We don't need sys/cdefs.h for __CONCAT here.imp2010-07-151-2/+0
* Use cpuregs.h spellings over the cpu.h spellings.imp2010-07-141-2/+2
* Remove the unused part of cpu.h now that the rest of the tree has beenimp2010-07-141-200/+3
* union cpuprid is also unused nowimp2010-07-131-22/+0
* Add INFO config register from mips32/64 landimp2010-07-131-0/+2
* Define break value for ddb.imp2010-07-131-15/+16
* cpu_id and fpu_id are unused, except to be set early in the boot code.imp2010-07-132-10/+0
* Remove obsolete define "COPY_SIGCODE". This is unused in FreeBSD.imp2010-07-131-6/+0
* Merge jmallett@'s n64 work into HEADjchandra2010-07-121-0/+16
* Move KSEG address definitions from cpu.h to cpuregs.h with the otherjchandra2010-07-122-19/+25
* Use 64 bit type for rqb_word_t in n64 kernel.jchandra2010-07-081-2/+11
* Merge jmallett@'s n64 work into HEAD - changeset 8jchandra2010-07-082-10/+9
* Remove save/restore of PageMask in tlb.c functions introduced in r209243.jchandra2010-07-021-1/+2
* Merge jmallett@'s n64 work into HEAD - changeset 7jchandra2010-06-244-13/+31
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