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* MIPS changes for Netlogic XLP support.jchandra2011-07-163-2/+6
* MFCattilio2011-05-131-0/+2
* Fix a brain-o in platform_cpu_mask() by just specifying a possibleattilio2011-05-131-1/+1
* Add the cpuset_t conversion for mips.attilio2011-05-134-4/+8
* Fix the _long() rappresentation on mips by casting the long argumentsattilio2011-05-131-23/+38
* o) Properly size caches and TLB on Octeon.jmallett2011-03-161-5/+8
* Increase NKPT in case of n32 and n64 to support more physical memory.jchandra2011-03-011-0/+4
* Remove pmap fields that are either unused or not fully implemented.alc2011-02-171-2/+0
* Allow the platform code to return a bitmask of running cores rather than justjmallett2011-02-121-2/+2
* o) Cavium Octeon doesn't need nop barriers.jmallett2011-02-061-0/+42
* Replace __LP64__ with __mips_n64. This partly reverts r217147.tijl2011-02-044-12/+12
* Implement sf_buf using direct map (XKPHYS) in MIPS n64.jchandra2011-01-271-0/+28
* Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().jkim2011-01-171-1/+4
* Support for 64 bit PTEs on n32 and n64 compilation.jchandra2011-01-135-64/+114
* Cleanup physical address and PTE types on MIPS.jchandra2011-01-132-5/+5
* Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.kib2011-01-091-11/+0
* White space changes to align comments. The mips and powerpc _inttypes.htijl2011-01-081-110/+110
* Rename PRIreg helper macro to PRIptr to better reflect its use. Registerstijl2011-01-081-46/+48
* On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather thantijl2011-01-083-38/+28
* On 32 bit architectures define (u)int64_t as (unsigned) long long insteadtijl2011-01-081-11/+6
* Fix types of some values in machine/_limits.h.tijl2011-01-081-6/+4
* Remove unused support for 64 bit long on 32 bit architectures.tijl2011-01-071-11/+3
* Add AT_STACKPROT elf aux vector. Will be used to inform rtld about thekib2011-01-071-1/+2
* Correct an 8-year-old typo which reliably leads to typo after typo today:jmallett2011-01-041-42/+43
* o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.jmallett2011-01-041-0/+9
* UMA_MD_SMALL_ALLOC for mips.jchandra2010-12-092-0/+5
* 1. Fix off by one errors in calls to MIPS_DIRECT_MAPPABLE, reported by alc@jchandra2010-12-031-6/+0
* Fixup for r216141, dump_add_page needs to be non-static now.jchandra2010-12-031-2/+4
* Revert r216134. This checkin broke platforms where bus_space are macros:brucec2010-12-031-67/+8
* Disallow passing in a count of zero bytes to the bus_space(9) functions.brucec2010-12-021-8/+67
* Set MACHINE_ARCH based on ABI and endianness.jmallett2010-11-281-1/+17
* - Remove <machine/mutex.h>. Most of the headers were empty, and thejhb2010-11-091-2/+0
* - Add minidump support for FreeBSD/mipsgonzo2010-11-073-0/+10
* Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.neel2010-09-221-0/+1
* Get rid of the unnecessary redirection of 'is_cacheable_mem()' toneel2010-09-171-3/+1
* Get rid of unused macros.neel2010-09-171-29/+0
* Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistentneel2010-09-151-1/+1
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+0
* The functions in sys/mips/mips/psraccess.S can be implemented withjchandra2010-09-132-5/+19
* Remove misleading comment in pte.h. MIPS PTE entries are software managedjchandra2010-08-301-3/+0
* Apply MIPS pmap clean up patch from alc@ (with minor change to KASSERT):jchandra2010-08-291-5/+0
* Whitespace fixes in mips/include, remove unused 'struct tlb' from locore.hjchandra2010-08-276-51/+49
* MIPS n64 support - continued...jchandra2010-08-182-11/+25
* Supply some useful information to the started image using ELF aux vectors.kib2010-08-171-1/+7
* Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.jchandra2010-08-132-2/+2
* Implement pmap changes suggested by alc@:jchandra2010-08-121-3/+1
* Update various places that store or manipulate CPU masks to use cpumask_tjhb2010-08-111-1/+1
* Add parentheses around the argument 'x' used in the __bswapXX(x) macros. Revertneel2010-08-111-6/+6
* - Consolidate the the cache coherence attribute definitions in a single place.neel2010-08-072-15/+66
* Add a new ipi_cpu() function to the MI IPI API that can be used to send anjhb2010-08-061-0/+1
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