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* Make octeon_ap_boot 64 bits to handle MAXCPU up to 64.marcel2011-08-052-12/+26
* MFCattilio2011-06-041-137/+194
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| * Add support for True IDE mode to the Octeon CF driver. This mode isimp2011-06-041-137/+194
* | Fix a brain-o in platform_cpu_mask() by just specifying a possibleattilio2011-05-131-6/+4
* | Add the cpuset_t conversion for mips.attilio2011-05-131-2/+12
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* - Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOPmarius2011-05-031-7/+3
* o) Set MAC addresses starting at the MAC base for all management ports, notjmallett2011-03-164-39/+34
* o) Tear down receive interrupt on detach.jmallett2011-03-164-7/+7
* o) Clean up FPA pools on module unload.jmallett2011-03-162-9/+47
* The Lanner MR-730 uses the first two MACs at its MAC base for the 10/100jmallett2011-02-122-4/+37
* Allow the platform code to return a bitmask of running cores rather than justjmallett2011-02-121-3/+3
* If there is no WQE available for a packet that needs segmentation, drop itjmallett2011-01-201-1/+6
* Remove some compile-time options from the driver, particularly async IOBDMAjmallett2011-01-204-114/+19
* Fix build by changing format for size_t to %jdgonzo2011-01-201-14/+14
* Don't do a device_identify to add uart0, it's already hinted.jmallett2011-01-191-8/+0
* Save the CPU model, the board and the CPU clock rate so they are reported byimp2011-01-171-9/+16
* Remove unneeded includes of <sys/linker_set.h>. Other headers that usejhb2011-01-112-2/+0
* Initialize PCIe buses and add preliminary support for 64-bit BARs.jmallett2011-01-111-215/+321
* Count output bytes and packets.jmallett2011-01-102-2/+8
* Shorten device name so it fits into vmstat -i.jmallett2011-01-101-3/+3
* o) Free mbufs in error cases.jmallett2011-01-101-0/+6
* o) Expand the CIU driver to be aware of newly-allocated parts of the IRQ range.jmallett2011-01-104-1/+525
* Now that we correctly enable rx interrupts on all cores, performance has gottenjmallett2011-01-091-1/+22
* o) Remove some unused local definitions of IP protocol numbers.jmallett2011-01-092-11/+10
* o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.jmallett2011-01-041-83/+99
* o) Unmask Central Interrupt Unit interrupts on APs, too.jmallett2011-01-041-4/+5
* When allocating memory from bootmem for the kernel to use, try to leave aboutjmallett2010-12-281-0/+8
* o) Add support for the Lanner MR-321X/MR-325, which is just a modified MR-320.jmallett2010-12-161-0/+1
* - dump_avail layout should be sequence of [start, end)gonzo2010-12-091-4/+2
* - Populate dump_avail with proper values from phys_availgonzo2010-12-091-1/+9
* Add interrupt describing and binding to CIU.jmallett2010-12-011-1/+115
* Run all poll requests through a single function that can either do the genericjmallett2010-11-307-63/+43
* Display some Octeon 2 features and a feature for distinguishing between PCIejmallett2010-11-301-0/+3
* Don't free the work queue entry that we're using to hold the scatter-gatherjmallett2010-11-291-4/+8
* Merge Cavium Octeon SDK 2.0 Simple Executive; this brings some fixes and newjmallett2010-11-284-21/+69
* - Add watchdog driver for Cavium Octeon. At the moment onlygonzo2010-11-283-0/+308
* o) Remove some commented out or unimplemented code.jmallett2010-11-289-364/+89
* Remove unused and broken code to implement POW send and POW-only devices; ajmallett2010-11-285-232/+5
* Use if_transmit to avoid ifq locking in transmit path.jmallett2010-11-271-26/+15
* Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mipsimp2010-11-131-0/+2
* Don't attach the PCI bus driver if the board we're being run on has PCIe. Thejmallett2010-11-031-0/+2
* Declare the CF GEOM class so that g_modevent will get called, the class willjmallett2010-11-021-0/+2
* Convert the PHY drivers to honor the mii_flags passed down and convertmarius2010-10-151-6/+6
* Keep polling at 50hz as long as link state is changing.jmallett2010-10-131-3/+15
* o) Make it possible to attach a PHY directly to an octe device rather thanjmallett2010-10-137-47/+811
* o) Allow devices to override the MDIO read and write functions presented tojmallett2010-10-028-1/+231
* Rather than shifting offsets by three, set register offset to 3. All ourjmallett2010-10-023-16/+15
* Remove extra cpu setting and commented-out devices, some of which don't exist.jmallett2010-10-021-12/+0
* Give devices lots of time to settle around programming BARs and commandjmallett2010-09-271-0/+4
* o) Program the Lanner MR-320 for 32-bit mode, too.jmallett2010-09-271-14/+77
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