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* Fix missing path conversion from the previous commit to shuffle mdio around.adrian2015-12-271-1/+1
* [qca953x] remove unneeded initialisation.adrian2015-12-151-1/+1
* [ar71xx] always count interrupts, spurious or otherwise.adrian2015-12-151-4/+2
* [arge] add a comment about needing mdio busses in order to use the interface.adrian2015-12-151-0/+5
* Add QCA9533 to the list of SoCs that require IRQ's be ACKed.adrian2015-11-161-0/+2
* Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros.adrian2015-11-169-0/+683
* Remove this; it's also in sys/conf/files.mips.adrian2015-11-031-2/+0
* arge_mdio: fix barriers; correctly check MII indicator register.adrian2015-10-301-21/+29
* arge: fix barrier macro.adrian2015-10-301-1/+1
* arge: attempt to close a transmit race by only enabling the descriptor at the...adrian2015-10-301-1/+22
* arge: just use 1U since it's a 32 bit unsigned destination value.adrian2015-10-301-1/+1
* arge: do an explicit flush between updating the TX ring and starting transmit.adrian2015-10-301-0/+3
* arge_mdio: add explicit read barriers for MDIO_READs.adrian2015-10-301-2/+7
* arge: ensure there's enough space in the TX ring before attempting toadrian2015-10-301-1/+1
* arge: do a read-after-write on all arge register writes, not just MDIO writes.adrian2015-10-301-4/+2
* Oops - use the wrong array offset.adrian2015-10-281-1/+1
* Add some debugging code (under ARGE_DEBUG) that counts each interrupt source.adrian2015-10-282-0/+37
* arge(4): flip this on for AR9344 SoCs.adrian2015-10-241-0/+3
* arge: use 1-byte TX and RX alignment for AR9330/AR9331.adrian2015-10-221-0/+2
* arge: Remove the debugging printf that snuck in.adrian2015-10-211-5/+0
* arge: don't do the rx fixup copy and just offset the mbuf by 2 bytesadrian2015-10-211-2/+29
* if_arge: fix up TX workaround; add TX/RX requirements for busdma; add statsadrian2015-10-182-22/+119
* Remove more unused variables leading to compile time errors.bz2015-09-172-2/+0
* Remove unused variable leading to compile errors.bz2015-09-171-1/+0
* Add domain support to PCI bus allocationzbb2015-09-163-3/+3
* Populate hw.model with the CPU model information.adrian2015-07-141-0/+4
* Reshuffle all of the DDR flush operations into a single switch/mux,adrian2015-07-0413-115/+152
* Oops - fix typo.adrian2015-07-031-2/+2
* Enable setting the QCA955x GPIO output mux configuration.adrian2015-07-031-4/+2
* Add register defines for the QCA955x DDR flush and GPIO control.adrian2015-07-031-0/+11
* Add initial support for the QCA955x PCIe host controller.adrian2015-05-192-0/+607
* Add support for the uart classes to set their default register shift value.andrew2015-04-111-1/+2
* Begin moving support for board MAC addresses over to being explicitly defined.adrian2015-03-284-49/+214
* Add GPIO function mux configuration for AR934x SoCs.adrian2015-03-211-0/+59
* add QCA955x PCIe configuration registers.adrian2015-03-211-0/+10
* Note that the AR724x PCIe registers are actually from the PCI_CTRLadrian2015-03-211-1/+1
* Use ar71xx_mac_addr_random_init() instead of a hand-rolled randomadrian2015-03-151-9/+2
* Start fleshing out some MAC address helper functions.adrian2015-03-153-0/+146
* Modify the if_arge code to use a /fixed/ media mode when it's configured.adrian2015-03-081-6/+38
* Add ethernet MAC DDR flush hookups for QCA955x.adrian2015-03-041-4/+5
* Add DDR flush registers for QCA955x.adrian2015-03-041-0/+7
* [QCA955x] make the USB EHCI interrupts shareable.adrian2015-03-021-1/+1
* Add initial QCA955x support to if_arge.c.adrian2015-03-021-1/+21
* Add a MII mode for SGMII.adrian2015-03-021-0/+1
* Add very initial QCA955x awareness to the GPIO code.adrian2015-03-011-3/+11
* Flesh out some more QCA955x ethernet PLL setup.adrian2015-03-011-28/+10
* Add Ethernet PLL values for the QCA955x.adrian2015-03-011-0/+5
* Make QCA955X_GMAC_REG_ETH_CFG defined like most other registers like this.adrian2015-03-011-1/+1
* Add QCA955x support to the EHCI setup path.adrian2015-03-011-0/+4
* The linux driver code for the MDIO bus does a read-after-writesbruno2015-02-021-2/+14
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