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* add QCA955x PCIe configuration registers.adrian2015-03-211-0/+10
* Note that the AR724x PCIe registers are actually from the PCI_CTRLadrian2015-03-211-1/+1
* Use ar71xx_mac_addr_random_init() instead of a hand-rolled randomadrian2015-03-151-9/+2
* Start fleshing out some MAC address helper functions.adrian2015-03-153-0/+146
* Modify the if_arge code to use a /fixed/ media mode when it's configured.adrian2015-03-081-6/+38
* Add ethernet MAC DDR flush hookups for QCA955x.adrian2015-03-041-4/+5
* Add DDR flush registers for QCA955x.adrian2015-03-041-0/+7
* [QCA955x] make the USB EHCI interrupts shareable.adrian2015-03-021-1/+1
* Add initial QCA955x support to if_arge.c.adrian2015-03-021-1/+21
* Add a MII mode for SGMII.adrian2015-03-021-0/+1
* Add very initial QCA955x awareness to the GPIO code.adrian2015-03-011-3/+11
* Flesh out some more QCA955x ethernet PLL setup.adrian2015-03-011-28/+10
* Add Ethernet PLL values for the QCA955x.adrian2015-03-011-0/+5
* Make QCA955X_GMAC_REG_ETH_CFG defined like most other registers like this.adrian2015-03-011-1/+1
* Add QCA955x support to the EHCI setup path.adrian2015-03-011-0/+4
* The linux driver code for the MDIO bus does a read-after-writesbruno2015-02-021-2/+14
* Implement GPIO_GET_BUS() method for all GPIO drivers.loos2015-01-312-4/+21
* Replace spaces with tabs, this will easier future changes on softcloos2015-01-311-6/+6
* Clean up and fix the device detach routine and the failure path on GPIOloos2015-01-311-6/+10
* Make the apb.c code optional behind ar71xx_apb rather than standard.adrian2015-01-061-1/+1
* Add an APB base/size for the QCA955X for an upcoming QCA955x specificadrian2015-01-061-0/+13
* The QCA955x USB init path doesn't require any of this, so delete it.adrian2015-01-061-19/+0
* Add 64-bit DMA support in the XHCI controller driver.hselasky2015-01-052-0/+2
* Remove the remnants of the OpenWRT/Linux bits that this was based offadrian2015-01-051-10/+0
* Oops - missed refclk.adrian2015-01-051-2/+1
* Add initial Qualcomm Atheros QCA955x SoC support.adrian2015-01-054-0/+502
* ACK interrupts on the new SoCs.adrian2015-01-051-0/+2
* add QCA955x SoC types.adrian2015-01-051-1/+3
* Add QCA955x series register definitions.adrian2015-01-051-0/+183
* Add a GPIO output mux configuration method.adrian2015-01-032-0/+40
* Add AR934x specific GPIO functions and output MUX configuration.adrian2015-01-031-0/+22
* Add AR934x GPIO function configuration.adrian2015-01-031-0/+6
* Moves all the duplicate code to a single function.loos2014-11-181-9/+1
* Make the GPIO children attach to the first unit available and not only toloos2014-10-281-2/+3
* Follow up to r225617. In order to maximize the re-usability of kernel codedavide2014-10-161-5/+5
* Fix the AR724x PCIe glue to correctly probe the BAR on AR7240 devices.adrian2014-09-281-3/+11
* Fix the ar724x PCI config space register read.adrian2014-09-281-4/+6
* Mechanically convert to if_inc_counter().glebius2014-09-191-2/+2
* Commit some sins in the name of "oh god oh god I don't really want toadrian2014-07-271-60/+11
* Properly advertise that if_arge can handle long frames (if_arge is set toloos2014-07-031-0/+3
* Fix various NIC drivers to properly cleanup static DMA resources.jhb2014-06-111-8/+6
* Do not configure all pins as outputs as this can lead to short circuits whenloos2014-05-101-4/+8
* Remove an old mistake of mine. This has sneak in the code i sent to gonzoloos2014-05-101-10/+0
* Add support for reading RouterBoard's memory which is passed by the loaderloos2014-05-091-0/+36
* When a GPIO pin is set to be turned on by kernel hints (hint.gpio.X.pinon)loos2014-05-091-1/+4
* Extend the Atheros SoC support to include a method to enable/disableadrian2014-03-182-0/+36
* Add the AR934x NAND flash controller register definitions.adrian2014-03-181-0/+177
* Implement apb_print_child().adrian2014-03-171-0/+34
* The AR71xx has APB interrupts in the MISC registers from 0-7, lateradrian2014-03-161-4/+6
* * Handle the three other timer interrupts for now, from the AR724xadrian2014-03-161-3/+3
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