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* Add the AR933x SoC GPIO pin count limitation.adrian2013-05-021-0/+5
* Fix undefined behaviour in several gpio_pin_setflags() routines (underdim2013-04-131-2/+2
* Implement USB device reset and poweron.adrian2013-04-051-35/+6
* Fix AR933x USB support - this needs the same controller initialisationadrian2013-04-051-0/+2
* Implement the AR933x ethernet support.adrian2013-04-053-1/+24
* Implement the AR933x interrupt driven UART code.adrian2013-04-051-46/+103
* AR9330/AR9331 also needs to ACK the APB interrupt register, same asadrian2013-04-051-0/+2
* * Add AR9330/AR9331 to the soc identifier enum;adrian2013-04-052-1/+5
* Implement AR933x polled IO uart bus code.adrian2013-04-041-316/+112
* AR933x CPU device improvements:adrian2013-03-301-70/+95
* AR933x UART updates:adrian2013-03-301-11/+8
* For the AR933x UART, the serial clock is not the AHB clock, it's theadrian2013-03-292-2/+2
* * Fix clock register definitionsadrian2013-03-291-2/+5
* Print out the platform reference frequency.adrian2013-03-291-2/+2
* Tie in the AR933x support into -HEAD.adrian2013-03-282-3/+19
* Bring over the initial, CPU-only UART support for the AR933x SoC.adrian2013-03-284-0/+1081
* Fix the AR933x platform device start/stop code.adrian2013-03-281-10/+4
* Commit initial (unfinished!) support for the AR933x series of embeddedadrian2013-03-274-0/+468
* Add the reference clock for each supported chip.adrian2013-03-274-0/+9
* Mips Atheros AR71XX: make PCI base slot configurable through hints.monthadar2013-01-061-2/+15
* Mechanically substitute flags from historic mbuf allocator withglebius2012-12-051-2/+2
* Make MIPS24k PMC optional on "hwpmc_mips24k."adrian2012-11-171-1/+1
* Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx.adrian2012-11-171-2/+2
* Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registersadrian2012-08-261-0/+4
* The GPIO drivers were initialising their mutexes with type ofrpaulo2012-08-171-2/+1
* Disable setting the MII port speed.adrian2012-05-041-0/+12
* Fix a totally bone-headed, last minute bounds check snafu that somehowadrian2012-05-031-3/+5
* Implement PLL configuration override support, similar to what openwrtadrian2012-05-022-3/+57
* Allow the MII mode to be overridden via 'hint.arge.X.miimode'.adrian2012-05-022-0/+25
* Add a missing newline.adrian2012-05-021-0/+1
* Further ar71xx MII support improvements.adrian2012-05-025-52/+61
* MII related infrastructure changes.adrian2012-05-025-0/+70
* Introduce an enum which encapsulates the PHY interface types that can beadrian2012-05-021-1/+7
* Add in the MII configuration parameters for the AR71xx.adrian2012-05-011-4/+15
* Break out the arge MDIO bus code into an optional argemdio device.adrian2012-05-013-115/+220
* Migrate ARGE_DEBUG to opt_arge.h.adrian2012-05-011-0/+2
* Allow for a default GPIO pin "high", which is required for some boardsadrian2012-04-201-1/+9
* Introduce the matching PCI ath(4) fixup code from ar71xx_pci intoadrian2012-04-205-83/+275
* Style(9) and white space fixes.adrian2012-04-171-31/+26
* Protect the PCI space registers behind a mutex.adrian2012-04-171-1/+22
* The AR913x MII speed configuration matches the AR71xx MII configuration.adrian2012-04-153-9/+4
* Fix the mask logic when reading PCI configuration space registers.adrian2012-04-151-2/+6
* (ab)Use the firmware API to store away EEPROM calibration data foradrian2012-04-131-6/+72
* Remove an unused variable. Grr.adrian2012-04-131-1/+1
* Sync this code against what's in OpenWRT trunk.adrian2012-04-131-27/+28
* Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.jmallett2012-03-291-1/+1
* Rework MIPS PMC code:gonzo2012-03-221-0/+2
* Move PMC hook invocation to cpu_intr. The idea is the same as with ast()gonzo2012-03-221-20/+3
* - Fix logic for detection if further processing of PMC should be performed.gonzo2012-03-181-6/+14
* style(9) changes.adrian2012-03-171-9/+10
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