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* MFC r274670, r274671, r276168:loos2015-02-141-9/+1
* MFC r273799:loos2015-02-141-2/+3
* MFC r266969 and r276717:hselasky2015-02-052-0/+2
* MFC r257334, r257336, r257337, r257338, r257341, r257342, r257343, r257370,ian2014-05-147-7/+7
* MFC: r260889, r260890, r260911:imp2014-03-011-0/+32
* MFC r258779,r258780,r258787,r258822:eadler2014-02-043-5/+27
* Add some missing AR934x register definitions.adrian2013-10-092-0/+45
* Fix interrupt handling from the APB periperals (ie, UART) - itadrian2013-10-091-0/+3
* Fix the AR933x CPU UART support by using the correct clock when calculatingadrian2013-09-211-2/+8
* Remove the hardcoded limit for the number of gpio_pins that can be used.loos2013-09-062-2/+10
* Fix an off-by-one bug in ar71xx_gpio and bcm2835_gpio which makes the lastloos2013-09-061-1/+1
* Fix the leakage of dma tags on if_arge. The leak occur when arge_start()loos2013-09-061-0/+26
* Prevent the full restart cycle every time arge_start() is called. Onlyloos2013-08-291-1/+2
* Make ar71xx_spi attach the next free unit of spibus and not only spibus0.loos2013-08-281-1/+1
* Some vendors store the mac addresses of arge(4) as a literal sring in thesbruno2013-08-231-4/+17
* Add a missing break.adrian2013-08-121-0/+1
* Implement some initial AR934x support routines.adrian2013-07-214-0/+394
* Teach the GPIO code about the AR934x GPIO register and pin counts.adrian2013-07-211-2/+17
* Use the UART frequency when programming the UART clock.adrian2013-07-214-4/+4
* Initialise the watchdog and UART frequencies.adrian2013-07-214-0/+12
* Add two new CPU specific definitions - the watchdog clock frequency andadrian2013-07-211-1/+5
* Import the initial SoC register definitions for the AR934x MIPS74k SoC.adrian2013-07-081-0/+156
* Add AR9341, AR9342, AR9344 SoC types.adrian2013-07-081-0/+3
* Add the AR933x SoC GPIO pin count limitation.adrian2013-05-021-0/+5
* Fix undefined behaviour in several gpio_pin_setflags() routines (underdim2013-04-131-2/+2
* Implement USB device reset and poweron.adrian2013-04-051-35/+6
* Fix AR933x USB support - this needs the same controller initialisationadrian2013-04-051-0/+2
* Implement the AR933x ethernet support.adrian2013-04-053-1/+24
* Implement the AR933x interrupt driven UART code.adrian2013-04-051-46/+103
* AR9330/AR9331 also needs to ACK the APB interrupt register, same asadrian2013-04-051-0/+2
* * Add AR9330/AR9331 to the soc identifier enum;adrian2013-04-052-1/+5
* Implement AR933x polled IO uart bus code.adrian2013-04-041-316/+112
* AR933x CPU device improvements:adrian2013-03-301-70/+95
* AR933x UART updates:adrian2013-03-301-11/+8
* For the AR933x UART, the serial clock is not the AHB clock, it's theadrian2013-03-292-2/+2
* * Fix clock register definitionsadrian2013-03-291-2/+5
* Print out the platform reference frequency.adrian2013-03-291-2/+2
* Tie in the AR933x support into -HEAD.adrian2013-03-282-3/+19
* Bring over the initial, CPU-only UART support for the AR933x SoC.adrian2013-03-284-0/+1081
* Fix the AR933x platform device start/stop code.adrian2013-03-281-10/+4
* Commit initial (unfinished!) support for the AR933x series of embeddedadrian2013-03-274-0/+468
* Add the reference clock for each supported chip.adrian2013-03-274-0/+9
* Mips Atheros AR71XX: make PCI base slot configurable through hints.monthadar2013-01-061-2/+15
* Mechanically substitute flags from historic mbuf allocator withglebius2012-12-051-2/+2
* Make MIPS24k PMC optional on "hwpmc_mips24k."adrian2012-11-171-1/+1
* Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx.adrian2012-11-171-2/+2
* Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registersadrian2012-08-261-0/+4
* The GPIO drivers were initialising their mutexes with type ofrpaulo2012-08-171-2/+1
* Disable setting the MII port speed.adrian2012-05-041-0/+12
* Fix a totally bone-headed, last minute bounds check snafu that somehowadrian2012-05-031-3/+5
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