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path: root/sys/mips/atheros/if_argevar.h
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* Migrate if_arge to use the PLL cpuops.adrian2010-08-191-2/+0
* Remove the now-unused DDR flush register value.adrian2010-08-191-1/+0
* Add TX-path aligned/unaligned stats for if_arge.adrian2010-07-081-0/+4
* Introduce a sysctl block for if_arge and, for now, a blank debug sysctladrian2010-07-081-0/+3
* - Handle multiphy MAC case: create interface withgonzo2009-11-121-1/+8
* - Access to all 5 PHYs goes through registers in MAC0 memorygonzo2009-11-081-0/+10
* - Fix initialization of PLL registers (different shifts forgonzo2009-11-061-0/+1
* - Remove noisy "Implement me" stubsgonzo2009-11-041-0/+1
* - Revert changes accidentally killed by merge operationgonzo2009-04-141-0/+138
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