Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Note that the AR724x PCIe registers are actually from the PCI_CTRL | adrian | 2015-03-21 | 1 | -1/+1 |
* | Use the correct bitshift operators for the GPIO definitions. | adrian | 2014-01-22 | 1 | -17/+17 |
* | Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC. | adrian | 2011-05-06 | 1 | -2/+0 |
* | Add some initial PCIe bridge support for the AR724x chipsets. | adrian | 2011-04-30 | 1 | -2/+22 |
* | Add the IP2 DDR flush handlers. | adrian | 2011-04-28 | 1 | -0/+1 |
* | Implement AR724x USB initialisation code. | adrian | 2011-03-31 | 1 | -0/+2 |
* | Add the missing AR724x DDR flush routines for if_arge0. | adrian | 2011-03-13 | 1 | -0/+3 |
* | Add some initial AR724X chipset support. | adrian | 2010-08-19 | 1 | -0/+3 |
* | Import initial AR91XX and AR724X CPU register definitions. | adrian | 2010-08-18 | 1 | -0/+81 |