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path: root/sys/mips/atheros/ar724x_chip.c
Commit message (Expand)AuthorAgeFilesLines
* Reshuffle all of the DDR flush operations into a single switch/mux,adrian2015-07-041-16/+13
* Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernetadrian2013-10-151-1/+1
* Initialise the watchdog and UART frequencies.adrian2013-07-211-0/+2
* Add the reference clock for each supported chip.adrian2013-03-271-0/+2
* Further ar71xx MII support improvements.adrian2012-05-021-2/+2
* MII related infrastructure changes.adrian2012-05-021-0/+9
* style(9) changes.adrian2012-03-171-9/+10
* Begin fleshing out MII clock rate configuration changes.adrian2012-03-171-0/+8
* Style(9) changes.adrian2011-12-131-43/+43
* Join chip depended methods for arge0 and arge1 into single call with unit.ray2011-11-271-18/+28
* Remove duplicate header includeskevlo2011-06-261-5/+3
* Add the IP2 DDR flush handlers.adrian2011-04-281-1/+8
* Implement AR724x USB initialisation code.adrian2011-03-311-1/+46
* Add the missing AR724x DDR flush routines for if_arge0.adrian2011-03-131-0/+2
* Add some initial AR724X chipset support.adrian2010-08-191-0/+165
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