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path: root/sys/mips/atheros/ar71xx_cpudef.h
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* Reshuffle all of the DDR flush operations into a single switch/mux,adrian2015-07-041-9/+13
* Add a GPIO output mux configuration method.adrian2015-01-031-0/+8
* Extend the Atheros SoC support to include a method to enable/disableadrian2014-03-181-0/+9
* Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernetadrian2013-10-151-0/+26
* Add two new CPU specific definitions - the watchdog clock frequency andadrian2013-07-211-1/+5
* Add the reference clock for each supported chip.adrian2013-03-271-0/+2
* Further ar71xx MII support improvements.adrian2012-05-021-3/+8
* MII related infrastructure changes.adrian2012-05-021-0/+6
* Begin fleshing out MII clock rate configuration changes.adrian2012-03-171-0/+6
* Join chip depended methods for arge0 and arge1 into single call with unit.ray2011-11-271-18/+6
* Tidy up the naming of the ip2 DDR flush routine, and add an inlineadrian2011-04-291-1/+6
* add the PLL set functions to cpuopsadrian2010-08-191-0/+10
* Bring over the first cut of the Atheros-specific SoC operations.adrian2010-08-181-0/+108
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