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* Replace mips/sentry5 with mips/broadcomlandonf2016-06-251-2/+0
| | | | | | | | | | | | | | | | | The delta between SENTRY5 and BCM was already small due to BCM being derived from SENTRY5; re-integrating the two avoids the maintenance overhead of keeping them both in sync with bhnd(4) changes. - Re-integrate minor SENTRY5 deltas in bcm_machdep.c - Modify uart_cpu_chipc to allow specifying UART debug/console flags via kenv and device hints. - Switch SENTRY5 to std.broadcom - Enabled CFI flash support for SENTRY5 Reviewed by: Michael Zhilin <mizkha@gmail.com> (Broadcom MIPS support) Approved by: re (gjb), adrian (mentor) Differential Revision: https://reviews.freebsd.org/D6897
* Reshuffle all of the DDR flush operations into a single switch/mux,adrian2015-07-041-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
* Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernetadrian2013-10-151-1/+2
| | | | | | | | | | | | | | | | | switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane.
* Initialise the watchdog and UART frequencies.adrian2013-07-211-0/+4
| | | | | | | | | For all pre-AR933x chips, the frequency is just the APB frequency. For the AR933x, the UART frequency is different but we just hacked around it. For the AR934x, there's a different PLL setting for these, so they have to be broken out.
* Add the reference clock for each supported chip.adrian2013-03-271-0/+3
| | | | Obtained from: Linux (openwrt)
* Fix a totally bone-headed, last minute bounds check snafu that somehowadrian2012-05-031-3/+5
| | | | | | I must've missed when booting a test kernel. This has been validated on the AR7161.
* Further ar71xx MII support improvements.adrian2012-05-021-25/+19
| | | | | | | | | | | | | | | * Flesh out the PLL configuration fetch function, which will return the PLL configuration based on the unit number and speed. * Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config function - pass in a 'pll' value instead. * Modify arge_set_pll() to: + fetch the PLL configuration + write the PLL configuration + update the MII speed configuration. This will allow if_arge to override the PLL configuration as required. Obtained from: Linux/Atheros/OpenWRT
* MII related infrastructure changes.adrian2012-05-021-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add a new method to set the MII mode - GMII, RGMII, RMII, MII. + arge0 supports all four (two for non-Gige interfaces.) + arge1 only supports two (one for non-gige interfaces.) * Set the MII clock speed when changing the MAC PLL speed. + Needed for AR91xx and AR71xx; not needed for AR724x. Tested: * AR71xx only, I'll do AR913x testing tonight and fix whichever issues creep up. TODO: * Implement the missing AR7242 arge0 PLL configuration, but don't adjust the MII speed accordingly. * .. the AR7240/AR7241 don't require this, so make sure it's not set accidentally. Bugs (not fixed here): * Statically configured arge speeds are still broken - investigate why that is on the AP96 board. Autonegotiate is working fine, but there still seems to be an occasionally heavy packet loss issue. Obtained from: Linux/Atheros/OpenWRT
* The AR913x MII speed configuration matches the AR71xx MII configuration.adrian2012-04-151-1/+1
| | | | | | | So share the code. Don't do it for the AR724x - that has a completely different set of PLL and MII configuration parameters.
* Begin fleshing out MII clock rate configuration changes.adrian2012-03-171-0/+41
| | | | | | | | | | | | These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined.
* Style(9) changes.adrian2011-12-131-26/+31
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* Join chip depended methods for arge0 and arge1 into single call with unit.ray2011-11-271-38/+33
| | | | Approved by: adrian (mentor)
* Remove duplicate header includeskevlo2011-06-261-5/+3
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* Add a missing DDR FIFO method for the ar71xx.adrian2011-04-301-1/+7
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* Implement PLL generalisation in preparation for use in if_arge.adrian2010-08-191-3/+37
| | | | | | | | * Add a function to write to the relevant PLL register * Break out the PLL configuration for the AR71XX into the CPU ops, lifted from if_arge.c. * Add the AR91XX PLL configuration ops, using the AR91XX register definitions.
* Add missing licence.adrian2010-08-191-0/+26
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* Preparation work for supporting the AR91xx and AR724x.adrian2010-08-191-0/+180
* Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
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