Commit message (Expand) | Author | Age | Files | Lines | |
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* | The AR71xx has APB interrupts in the MISC registers from 0-7, later | adrian | 2014-03-16 | 1 | -4/+6 |
* | - Add intr counters for APB interrupts | gonzo | 2009-11-18 | 1 | -0/+1 |
* | - Handle memory requests on apb level, do not pass them up to | gonzo | 2009-05-06 | 1 | -0/+1 |
* | - Revert changes accidentally killed by merge operation | gonzo | 2009-04-14 | 1 | -0/+48 |