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* Add bus_dmamap_load_mbuf_sg() to ia64scottl2005-01-152-6/+41
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* - Remove some OBE comments regarding cpu_exit(). cpu_exit() is no longerjhb2005-01-141-0/+1
| | | | | | | | the last action of kern_exit(). Instead, it is a MD callout to cleanup per-process state during exit. - Add notes of concern to Alpha and ia64 about the possible need to drop fp state in cpu_thread_exit() rather than in cpu_exit() since it is per-thread state rather than per-process.
* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-0662-63/+64
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* Further enhance the handling of misaligned loads and stores:marcel2005-01-023-23/+59
| | | | | | | | | | | | | | | | | | | | o implement double-extended and single precision loads and stores, o implement double precision stores, o replace the machdep.unaligned_print sysctl with debug.unaligned_print and change the default value to 0, o replace the machdep.unaligned_sigbus sysctl with debug.unaligned_test, o Remmove the fillfd() function. The function is trvial enough for inline assembly. The debug.unaligned_test sysctl is used to test the emulation of misaligned loads and stores. When PSR.ac is 0, the CPU will handle misaligned memory accesses itselfi and we don't get an exception for it. When PSR.ac is 1, the process needs to be signalled and we should not emulate. The sysctl takes effect when PSR.ac is 1 and tells us that we should emulate and not send a signal. PR: 72268 MFC after: 1 week
* Modify pmap_enter_quick() so that it expects the page queues to be lockedalc2004-12-231-3/+2
| | | | | | | | | | | on entry and it assumes the responsibility for releasing the page queues lock if it must sleep. Remove a bogus comment from pmap_enter_quick(). Using the first change, modify vm_map_pmap_enter() so that the page queues lock is acquired and released once, rather than each time that a page is mapped.
* In the common case, pmap_enter_quick() completes without sleeping.alc2004-12-151-0/+4
| | | | | | | | | | | | | | | | | | In such cases, the busying of the page and the unlocking of the containing object by vm_map_pmap_enter() and vm_fault_prefault() is unnecessary overhead. To eliminate this overhead, this change modifies pmap_enter_quick() so that it expects the object to be locked on entry and it assumes the responsibility for busying the page and unlocking the object if it must sleep. Note: alpha, amd64, i386 and ia64 are the only implementations optimized by this change; arm, powerpc, and sparc64 still conservatively busy the page and unlock the object within every pmap_enter_quick() call. Additionally, this change is the first case where we synchronize access to the page's PG_BUSY flag and busy field using the containing object's lock rather than the global page queues lock. (Modifications to the page's PG_BUSY flag and busy field have asserted both locks for several weeks, enabling an incremental transition.)
* Fix the last of the instability and the cause of the annoyingmarcel2004-12-121-2/+6
| | | | | | | | | | | | "vm_fault: fault on nofault entry, addr: %lx" panic. The problem was a stale PTE in the TLB that marked the page as not present, even though we had a good PTE in the VHPT. We typically don't yet insert PTEs in the TLB. We do that lazily. The CPU will look for the PTE in the VHPT when there's no PTE in the TLB. Unfortunately this doesn't handle the case of the stale PTE in the TLB. The quick fix is to invalidate the TLB (sloppily) when the VHPT doesn't contain a valid PTE. This is also the only case that may cause a PTE in the TLB that marks a page as non-present.
* Use primitive types to avoid creating an artificial header dependency:marcel2004-12-111-11/+11
| | | | | | | | o s/u_long/unsigned long/ o s/uint32_t/unsigned int/g o s/uint64_t/unsigned long/g Trigger case: multimedia/mpeg2codec
* Don't obtain the HCDP address directly from the bootinfo structure.marcel2004-12-082-0/+8
| | | | Use a function to keep the details at arms length from uart(4).
* Change gdb_cpu_setreg() to not take the value to which to set themarcel2004-12-012-2/+2
| | | | | | | | | | | | | | | | | | | | | specified register, but a pointer to the in-memory representation of that value. The reason for this is twofold: 1. Not all registers can be represented by a register_t. In particular FP registers fall in that category. Passing the new register value by reference instead of by value makes this point moot. 2. When we receive a G or P packet, both are for writing a register, the packet will have the register value in target-byte order and in the memory representation (modulo the fact that bytes are sent as 2 printable hexadecimal numbers of course). We only need to decode the packet to have a pointer to the register value. This change fixes the bug of extracting the register value of the P packet as a hexadecimal number instead of as a bit array. The quick (and dirty) fix to bswap the register value in gdb_cpu_setreg() as it has been added on i386 and amd64 can therefore be removed and has in fact been that. Tested on: alpha, amd64, i386, ia64, sparc64
* Whitespace fixes:marcel2004-11-281-33/+18
| | | | | | | o Remove a bogus comment that relates to alpha. o s/u_int64_t/uint64_t/g o Add bi_spare2 to make the internal padding explicit. o Move BOOTINFO_MAGIC after the field it applies to.
* Don't include sys/user.h merely for its side-effect of recursivelydas2004-11-273-4/+3
| | | | including other headers.
* Remove struct ia64_itir and use a plain old uint64_t instead.marcel2004-11-212-17/+12
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* Remove UAREA_PAGES.das2004-11-201-1/+0
| | | | Reviewed by: arch@
* U areas are going away, so don't allocate one for process 0.das2004-11-201-4/+1
| | | | Reviewed by: arch@
* user.h is included only to get pcb.h, so use the latter directly instead.das2004-11-201-1/+1
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* Remove the BR tag. When the machine doesn't have the DIG64 HCDPmarcel2004-11-141-1/+1
| | | | | | | | table with console settings, we now only need to know at which address the UART lives. Leaving the baudrate unspecified results in us using the baudrate at which the UART operates. This removes one parameter that can interfere with a successful installation out of the box.
* - Change the ddb paging "support" to use a variable (db_lines_per_page) tojhb2004-11-011-1/+1
| | | | | | | | | | | | | | | | | control the number of lines per page rather than a constant. The variable can be examined and changed in ddb as '$lines'. Setting the variable to 0 will effectively turn off paging. - Change db_putchar() to force out pending whitespace before outputting newlines and carriage returns so that one can rub out content on the current line via '\r \r' type strings. - Change the simple pager to rub out the --More-- prompt explicitly when the routine exits. - Add some aliases to the simple pager to make it more compatible with more(1): 'e' and 'j' do a single line. 'd' does half a page, and 'f' does a full page. MFC after: 1 month Inspired by: kris
* Use bioq_takefirst()phk2004-10-231-3/+1
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* Add new function ttyinitmode() which sets our systemwide defaultphk2004-10-181-6/+1
| | | | | | | | | | | | | | modes on a tty structure. Both the ".init" and the current settings are initialized allowing the function to be used both at attach and open time. The function takes an argument to decide if echoing should be enabled. Echoing should not be enabled for regular physical serial ports unless they are consoles, in which case they should be configured by ttyconsolemode() instead. Use the new function throughout.
* Print flags in the nexus for child devices.njl2004-10-141-0/+2
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* Move the code for halting the CPU (acpi_cpu_c1) into machdep files.njl2004-10-112-0/+9
| | | | | | This removes the last MD portion of acpi_cpu.c. MFC after: 2 weeks
* Add the Madison II, which is the second generation Madison. The Madison IImarcel2004-10-061-0/+3
| | | | | is model 2 in the Itanium 2 family and has up to 9MB of L3 cache and clocks higher than 1.5Ghz. There's no LV variant AFAICT.
* The physical address stored in the vm_page is page aligned. There is noalc2004-10-031-1/+1
| | | | | | need to mask off the page offset bits. (This operation made some sense prior to i386/i386/pmap.c revision 1.254 when we passed a physical address rather than a vm_page pointer to pmap_enter().)
* Eliminate unnecessary uses of PHYS_TO_VM_PAGE() from pmap_enter(). Thesealc2004-10-021-5/+2
| | | | | | | uses predate the change in the pmap_enter() interface that replaced the page's physical address by the address of its vm_page structure. The PHYS_TO_VM_PAGE() was being used to compute the address of the same vm_page structure that was being passed in.
* ...And fix WITNESS builds: declare syscallnames.marcel2004-09-261-0/+4
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* Fix INVARIANTS build: Include <machine/cpu.h>.marcel2004-09-261-0/+1
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* Move the IA-32 trap handling from trap() to ia32_trap(). Move themarcel2004-09-255-299/+373
| | | | | ia32_syscall() function along with it to ia32_trap.c. When COMPAT_IA32 is not defined, we'll raise SIGEMT instead.
* Redefine a PTE as a 64-bit integral type instead of a struct ofmarcel2004-09-236-258/+212
| | | | | bit-fields. Unify the PTE defines accordingly and update all uses.
* s/u_int#_t/uint#_t/gmarcel2004-09-221-20/+20
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* For the atomic_{add|clear|set|subtract} family of inlines, return themarcel2004-09-221-2/+4
| | | | | | old or previous value instead of void. This is not as is documented in atomic(9), but is API (and ABI) compatible and simply makes sense. This feature will primarily be used for atomic PTE updates in PMAP/ng.
* MFp4: various style fixes, includingmarcel2004-09-221-248/+239
| | | | | | | | o s/u_int/uint/g o s/#define<sp>/#define<tab>/g o indent macro definitions o Improve vertical spacing o Globally align line continuation character
* - Add support for "paging" in stack trace output. That is, when you dojhb2004-09-201-2/+4
| | | | | | | | | | | | | a stack trace from ddb, the output will pause with a '--More--' prompt every 18 lines. If you hit Enter, it will print another line and prompt again. If you hit space it will output another page and then prompt. If you hit 'q' or 'x' it will abort the rest of the stack trace. - Fix the sparc64 userland stack trace to honor the total count of lines to print. This is useful if your trace happens to walk back onto 0xdeadc0de and gets stuck in an endless loop. MFC after: 1 month Tested on: i386, alpha, sparc64
* MFp4:marcel2004-09-198-199/+353
| | | | | | Completely remove the remaining EFI includes and add our own (type) definitions instead. While here, abstract more of the internals by providing interface functions.
* Release the page queues lock earlier in pmap_protect() and pmap_remove() inalc2004-09-181-3/+2
| | | | order to reduce contention.
* Provide our own FPSWA definitions, instead of depending on the Intelmarcel2004-09-174-50/+55
| | | | | | EFI headers and put them all in <machine/fpu.h>. The Intel EFI headers conflict with the Intel ACPI headers (duplicate type definitions), so are being phased out in the kernel.
* Remove useless inclusion of <machine/fpu.h>marcel2004-09-171-1/+0
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* Add new a function isa_dma_init() which returns an errno when it failsphk2004-09-151-9/+8
| | | | | | | | | and which takes a M_WAITOK/M_NOWAIT flag argument. Add compatibility isa_dmainit() macro which whines loudly if isa_dma_init() fails. Problem uncovered by: tegge
* Catch up with other platforms: switch the default scheduler to 4BSD.marcel2004-09-122-2/+4
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* Fix a problem with tag->boundary inheritence that has existed since day onescottl2004-09-081-5/+5
| | | | | | | | | | | | | | and was propagated to nearly every platform. The boundary of the child needs to consider the boundary of the parent and pick the minimum of the two, not the maximum. However, if either is 0 then pick the appropriate one. This bug was exposed by a recent change to ATA, which should now be fixed by this change. The alignment and maxsegsz tag attributes likely also need a similar review in the near future. This is a MT5 candidate. Reviewed by: marcel Submitted by: sos (in part)
* Sync the busdma code with i386. The most tangible upshot is thatmarcel2004-09-081-207/+153
| | | | | | | | | | | the alignment and boundary constraints are being respected, which fixes the reported ATA problems with SiI chips. I consider the busdma implementation worrisome nonetheless. Not only is there too much MI code duplicated in MD files, there's a lot of questionable code. I smell a wholesale, cross-platform overhaul coming... MT5 candidate.
* Refactor a bunch of scheduler code to give basically the same behaviourjulian2004-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | but with slightly cleaned up interfaces. The KSE structure has become the same as the "per thread scheduler private data" structure. In order to not make the diffs too great one is #defined as the other at this time. The KSE (or td_sched) structure is now allocated per thread and has no allocation code of its own. Concurrency for a KSEGRP is now kept track of via a simple pair of counters rather than using KSE structures as tokens. Since the KSE structure is different in each scheduler, kern_switch.c is now included at the end of each scheduler. Nothing outside the scheduler knows the contents of the KSE (aka td_sched) structure. The fields in the ksegrp structure that are to do with the scheduler's queueing mechanisms are now moved to the kg_sched structure. (per ksegrp scheduler private data structure). In other words how the scheduler queues and keeps track of threads is no-one's business except the scheduler's. This should allow people to write experimental schedulers with completely different internal structuring. A scheduler call sched_set_concurrency(kg, N) has been added that notifies teh scheduler that no more than N threads from that ksegrp should be allowed to be on concurrently scheduled. This is also used to enforce 'fainess' at this time so that a ksegrp with 10000 threads can not swamp a the run queue and force out a process with 1 thread, since the current code will not set the concurrency above NCPU, and both schedulers will not allow more than that many onto the system run queue at a time. Each scheduler should eventualy develop their own methods to do this now that they are effectively separated. Rejig libthr's kernel interface to follow the same code paths as linkse for scope system threads. This has slightly hurt libthr's performance but I will work to recover as much of it as I can. Thread exit code has been cleaned up greatly. exit and exec code now transitions a process back to 'standard non-threaded mode' before taking the next step. Reviewed by: scottl, peter MFC after: 1 week
* Add aac(4) and aacp(4). The driver is 64-bit clean for roughly a yearmarcel2004-09-021-0/+2
| | | | now and has been mentioned on the freebsd-ia64 list.
* Remove an unneeded argument..julian2004-08-311-1/+1
| | | | | | | | | The removed argument could trivially be derived from the remaining one. That in turn should be the same as curthread, but it is possible that curthread could be expensive to derive on some syste,s so leave it as an argument. Having both proc and thread as an argumen tjust gives an opportunity for them to get out sync. MFC after: 3 days
* Remove sched_free_thread() which was only usedjulian2004-08-311-10/+0
| | | | | | | | in diagnostics. It has outlived its usefulness and has started causing panics for people who turn on DIAGNOSTIC, in what is otherwise good code. MFC after: 2 days
* Remove unnecessary check for curthread == NULL.alc2004-08-301-1/+1
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* s/ENTRY/ENTRY_NOPROFILE/g for particular functions that do not followmarcel2004-08-304-8/+8
| | | | | the C calling convention or are otherwise not regular functions. This allows us to boot a profiling kernel.
* Catch up with the drive-by renaming of IA32 to COMPAT_IA32. Missedmarcel2004-08-271-2/+2
| | | | | 11 days ago when all the other places were fixed and finally caught by the tinderbox run...
* Move the kernel-specific logic to adjust frompc from MI to MD. Formarcel2004-08-271-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | these two reasons: 1. On ia64 a function pointer does not hold the address of the first instruction of a functions implementation. It holds the address of a function descriptor. Hence the user(), btrap(), eintr() and bintr() prototypes are wrong for getting the actual code address. 2. The logic forces interrupt, trap and exception entry points to be layed-out contiguously. This can not be achieved on ia64 and is generally just bad programming. The MCOUNT_FROMPC_USER macro is used to set the frompc argument to some kernel address which represents any frompc that falls outside the kernel text range. The macro can expand to ~0U to bail out in that case. The MCOUNT_FROMPC_INTR macro is used to set the frompc argument to some kernel address to represent a call to a trap or interrupt handler. This to avoid that the trap or interrupt handler appear to be called from everywhere in the call graph. The macro can expand to ~0U to prevent adjusting frompc. Note that the argument is selfpc, not frompc. This commit defines the macros on all architectures equivalently to the original code in sys/libkern/mcount.c. People can take it from here... Compile-tested on: alpha, amd64, i386, ia64 and sparc64 Boot-tested on: i386
* The machine-independent parts of the virtual memory system always pass aalc2004-08-271-16/+0
| | | | | | | valid pmap to the pmap functions that require one. Remove the checks for NULL. (These checks have their origins in the Mach pmap.c that was integrated into BSD. None of the new code written specifically for FreeBSD included them.)
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