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* - Remove the old smp cpu topology specification with a new, more flexiblejeff2008-03-021-0/+7
* Re-sort options. While here:marcel2008-02-161-5/+8
* On Montecito processors, the instruction cache is in fact notmarcel2008-02-142-0/+19
* Allocate a stack for thread0 and switch to it before callingmarcel2008-02-043-21/+34
* Add a wrapper function that bound checks writes to the dump device.ru2008-01-281-6/+6
* Add COMPAT_FREEBSD7 and enable it in configs that have COMPAT_FREEBSD6.jhb2008-01-071-0/+1
* Add an access type parameter to pmap_enter(). It will be used to implementalc2008-01-031-2/+2
* Use correct function name in panic messageimp2008-01-031-1/+1
* Fix obsolete comment. pmap_remove_all is the function we're in.imp2008-01-031-2/+1
* Add configuration knobs for the superpage reservation system. Initially,alc2007-12-271-0/+7
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-251-1/+2
* Add stubs to unbreak LINT.jkoshy2007-12-071-0/+4
* Add a BSD disklabel backend to g_part:marcel2007-12-061-1/+1
* Break out stack(9) from ddb(4):rwatson2007-12-023-12/+58
* Remove the 'needbounce' variable from the _bus_dmamap_load_buffer()jhb2007-11-271-5/+2
* Define atomic_readandclear_ptr.jasone2007-11-271-0/+1
* Extend critical section coverage in the low-level interrupt handlers toscottl2007-11-211-1/+1
* Prevent the leakage of wired pages in the following circumstances:alc2007-11-171-0/+32
* o Rename cpu_thread_setup() to cpu_thread_alloc() to bettermarcel2007-11-142-2/+9
* generally we are interested in what thread did something asjulian2007-11-141-3/+3
* Fix for the panic("vm_thread_new: kstack allocation failed") andkib2007-11-052-2/+3
* Set PTE_ACCESSED in the PTE and before inserting it in the VHPT.marcel2007-10-161-2/+12
* The flushrs instruction must be the first in an instructionmarcel2007-10-161-0/+1
* Print instruction stops to improve analysis of dependencymarcel2007-10-161-0/+2
* Fix disassembly of the invala, itc, itr and hint instructionsmarcel2007-10-161-1/+1
* Use the correct expanded name for SCTP.brueffer2007-09-261-1/+1
* Change the management of cached pages (PQ_CACHE) in two fundamentalalc2007-09-251-2/+3
* It has been observed on the mailing lists that the different categoriesalc2007-09-151-2/+4
* Clear pending interrupts before we enable external interrupts.marcel2007-08-061-5/+20
* Keep interrupts disabled while handling external interrupts.marcel2007-08-063-73/+64
* In ia64_set_rr(), don't perform data serialization. This allowsmarcel2007-08-051-1/+1
* Replace "__asm __volatile()" by equivalent support functions frommarcel2007-08-041-6/+6
* Replace "__asm __volatile()" by equivalent support functions frommarcel2007-08-041-3/+5
* Replace "__asm __volatile()" by equivalent support functions frommarcel2007-08-041-16/+18
* Add required data-serialization after writing to cr.itm and cr.itv.marcel2007-08-041-0/+1
* Add ia64_srlz_d() and ia64_srlz_i() functions to aid in serialization.marcel2007-08-041-0/+12
* o Switch to physical addressing before dereferencing the VHPTmarcel2007-07-301-37/+62
* Add option EXCEPTION_TRACING, which enables KTR-like functionalitymarcel2007-07-302-1/+85
* Rework the interrupt code and add support for interrupt filteringmarcel2007-07-306-177/+239
* Explicitly map the VHPT on all processors. Previously we weremarcel2007-07-304-0/+27
* Add casts to some of the more commonly used pointer-type atomicmarcel2007-07-301-5/+14
* If clock_ct_to_ts fails to convert time time from the real time clock,dwmalone2007-07-231-1/+2
* Restore the value of ar.rnat after the assignment to ar.bspstore.marcel2007-07-161-3/+3
* dma_tag is a static structure. Testing for it being a NULL pointermarcel2007-07-091-1/+1
* Enable SCTP by default for GENERIC kernels in order to give itdelphij2007-06-141-0/+1
* Enable GEOM_PART_MBR by default. On ia64 this replaces GEOM_MBR.marcel2007-06-131-1/+1
* Add the machine-specific definitions for configuring the new physicalalc2007-06-102-1/+31
* Work around a firmware bug in the HP rx2660, where in ACPI an I/O portmarcel2007-06-102-3/+12
* Synchronize the instruction cache after writing to memory. This ismarcel2007-06-091-1/+5
* Add kdb_cpu_sync_icache(), intended to synchronize instructionmarcel2007-06-091-0/+15
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