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* Introduce the option VFS_ALLOW_NONMPSAFE and turn it on by default onattilio2011-11-081-0/+3
| | | | | | | | | | | | | | all the architectures. The option allows to mount non-MPSAFE filesystem. Without it, the kernel will refuse to mount a non-MPSAFE filesytem. This patch is part of the effort of killing non-MPSAFE filesystems from the tree. No MFC is expected for this patch. Tested by: gianni Reviewed by: kib
* Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.ed2011-11-074-5/+5
| | | | | | The SYSCTL_NODE macro defines a list that stores all child-elements of that node. If there's no SYSCTL_DECL macro anywhere else, there's no reason why it shouldn't be static.
* Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.ed2011-11-074-4/+4
| | | | This means that their use is restricted to a single C file.
* Adjust the debugger options slightly. This should help me do the rightkensmith2011-10-271-2/+5
| | | | | | | | thing when changing the debugging options as part of head becoming a new stable branch. It may also help people who for one reason or another want to run head but don't want it slowed down by the debugging support. Reviewed by: kib
* Move the debugging support to its own section. This matches what iskensmith2011-10-261-7/+9
| | | | | | | in the other architectures' GENERIC and makes removing it at the point we're creating a new stable branch a bit easier. Discussed with: marcel
* People porting FreeBSD to new architectures ought not have todas2011-10-211-0/+9
| | | | | | | | | | | | | implement a deprecated FPU control interface in addition to the standard one. To make this clearer, further deprecate ieeefp.h by not declaring the function prototypes except on architectures that implement them already. Currently i386 and amd64 implement the ieeefp.h interface for compatibility, and for fp[gs]etprec(), which doesn't exist on most other hardware. Powerpc, sparc64, and ia64 partially implement it and probably shouldn't, and other architectures don't implement it at all.
* Add a warning about why sbp(4) is commented out so that curious folkskensmith2011-10-191-0/+1
| | | | | | | are forewarned they might wind up with a hole in their foot if they decide to give it a try. Suggested by: dougb
* Comment out the sbp(4) driver for architectures that support it.kensmith2011-10-181-1/+1
| | | | | | | | | | | As part of the 8.0-RELEASE cycle this was done in stable/8 (r199112) but was left alone in head so people could work on fixing an issue that caused boot failure on some motherboards. Apparently nobody has worked on it and we are getting reports of boot failure with the 9.0 test builds. So this time I'll comment out the driver in head (still hoping someone will work on it) and MFC to stable/9. Submitted by: Alberto Villa <avilla at FreeBSD dot org>
* Remove unused define.kib2011-10-071-1/+0
| | | | MFC after: 1 month
* Remove locking of the vm page queues from several pmaps, which onlykib2011-09-281-2/+0
| | | | | | | | | protected the dirty mask updates. The dirty mask updates are handled by atomics after the r225840. Submitted by: alc Tested by: flo (sparc64) MFC after: 2 weeks
* In order to maximize the re-usability of kernel code in user space thiskmacy2011-09-162-4/+4
| | | | | | | | | | | | | patch modifies makesyscalls.sh to prefix all of the non-compatibility calls (e.g. not linux_, freebsd32_) with sys_ and updates the kernel entry points and all places in the code that use them. It also fixes an additional name space collision between the kernel function psignal and the libc function of the same name by renaming the kernel psignal kern_psignal(). By introducing this change now we will ease future MFCs that change syscalls. Reviewed by: rwatson Approved by: re (bz)
* Inline the syscallenter() and syscallret(). This reduces the time measuredkib2011-09-112-0/+4
| | | | | | | | by the syscall entry speed microbenchmarks by ~10% on amd64. Submitted by: jhb Approved by: re (bz) MFC after: 2 weeks
* Split the vm_page flags PG_WRITEABLE and PG_REFERENCED into atomickib2011-09-061-16/+16
| | | | | | | | | | | | | | | | | flags field. Updates to the atomic flags are performed using the atomic ops on the containing word, do not require any vm lock to be held, and are non-blocking. The vm_page_aflag_set(9) and vm_page_aflag_clear(9) functions are provided to modify afalgs. Document the changes to flags field to only require the page lock. Introduce vm_page_reference(9) function to provide a stable KPI and KBI for filesystems like tmpfs and zfs which need to mark a page as referenced. Reviewed by: alc, attilio Tested by: marius, flo (sparc64); andreast (powerpc, powerpc64) Approved by: re (bz)
* - Move the PG_UNMANAGED flag from m->flags to m->oflags, renaming the flagkib2011-08-091-14/+13
| | | | | | | | | | | | | | to VPO_UNMANAGED (and also making the flag protected by the vm object lock, instead of vm page queue lock). - Mark the fake pages with both PG_FICTITIOUS (as it is now) and VPO_UNMANAGED. As a consequence, pmap code now can use use just VPO_UNMANAGED to decide whether the page is unmanaged. Reviewed by: alc Tested by: pho (x86, previous version), marius (sparc64), marcel (arm, ia64, powerpc), ray (mips) Sponsored by: The FreeBSD Foundation Approved by: re (bz)
* Fix kernel core dumps now that the kernel is using PBVM. The basicmarcel2011-08-061-1/+4
| | | | | | | | | | | | | problem to solve is that we don't have a fixed mapping from kernel text to physical address so that libkvm can bootstrap itself. We solve this by passing the physical address of the bootinfo structure to the consumer as the entry point of the core file. This way, libkvm can extract the PBVM page table information and locate the kernel in the core file. We also need to dump memory chunks of type loader data, because those hold the kernel and the PBVM page table (among other things). Approved by: re (blanket)
* Follow-up commit: refactor pmap_kextract() to make it easier tomarcel2011-08-051-17/+28
| | | | | | | | | catch and debug issues like the one fixed in the previous commit: Replace all return statements with goto statements so that we end up at a single place with a value for the physical address. Print a message for all unknown KVA addresses. Approved by: re (blanket)
* Remove stray semicolon in pmap_kextract() that turned the conditionalmarcel2011-08-051-1/+1
| | | | | | | "return (0)" into an unconditional one and as such broke PBVM address queries -- such as during kernel core dumps. Approved by: re (blanket)
* Bump MAXCPU for amd64, ia64 and XLP mips appropriately.attilio2011-07-191-1/+1
| | | | | | | | | | | | | | | | | | | From now on, default values for FreeBSD will be 64 maxiumum supported CPUs on amd64 and ia64 and 128 for XLP. All the other architectures seem already capped appropriately (with the exception of sparc64 which needs further support on jalapeno flavour). Bump __FreeBSD_version in order to reflect KBI/KPI brekage introduced during the infrastructure cleanup for supporting MAXCPU > 32. This covers cpumask_t retiral too. The switch is considered completed at the present time, so for whatever bug you may experience that is reconducible to that area, please report immediately. Requested by: marcel, jchandra Tested by: pluknet, sbruno Approved by: re (kib)
* On 64 bit architectures size_t is 8 bytes, thus it should use an 8 bytesattilio2011-07-191-2/+2
| | | | | | | | | | storage. Fix the sintrcnt/sintrnames specification. No MFC is previewed for this patch. Reported, reviewed and tested by: marcel Approved by: re (kib)
* Add the possibility to specify from kernel configs MAXCPU value.attilio2011-07-191-0/+2
| | | | | | | | | | This patch is going to help in cases like mips flavours where you want a more granular support on MAXCPU. No MFC is previewed for this patch. Tested by: pluknet Approved by: re (kib)
* - Remove the eintrcnt/eintrnames usage and introduce the concept ofattilio2011-07-181-2/+5
| | | | | | | | | | | | | | | | sintrcnt/sintrnames which are symbols containing the size of the 2 tables. - For amd64/i386 remove the storage of intr* stuff from assembly files. This area can be widely improved by applying the same to other architectures and likely finding an unified approach among them and move the whole code to be MI. More work in this area is expected to happen fairly soon. No MFC is previewed for this patch. Tested by: pluknet Reviewed by: jhb Approved by: re (kib)
* Enable NEW_PCIB by default on ia64.jhb2011-07-181-0/+2
| | | | Approved by: re (kib), marcel
* Implement bus_adjust_resource() for the ia64 nexus driver.jhb2011-07-181-17/+34
| | | | | Reviewed by: marcel Approved by: re (kib)
* Don't assume pmap_mapdev() gets called only for memory mapped I/Omarcel2011-07-161-3/+29
| | | | | | | | | | | | addresses (i.e. uncacheable). ACPI in particular uses pmap_mapdev() rather excessively (number of calls) just to get a valid KVA. To that end, have pmap_mapdev(): 1. cache the last result so that we don't waste time for multiple consecutive invocations with the same PA/SZ. 2. find the memory descriptor that covers the PA and return NULL if none was found or when the PA is for a common DRAM address. 3. Use either a region 6 or region 7 KVA, in accordance with the memory attribute.
* Don't send EOI to the CPU before we handled the interrupt. This couldmarcel2011-07-162-4/+7
| | | | | | | | | | | | potentially trigger multiple pending interrupts for level-sensitive interrupts. However, the event timer interrupt does need EOI before being handled to avoid missing clock events. These conflicting requirements are handled by having the XIV handler inform the dispatch code whether or not it send EOI to the CPU. If not, the dispatch code will do it. This allows handlers to send EOI before doing potentially long-running activities, while still have a sensible default behaviour.
* Add a few more helper functions for working with memory descriptors:marcel2011-07-162-4/+54
| | | | | | o efi_md_find() - returns the md that covers the given address o efi_md_last() - returns the last md in the list o efi_md_prev() - returns the md that preceeds the given md.
* Implement basic support for memory attributes. At this time we onlymarcel2011-07-083-27/+121
| | | | | | | | | | | | | distinguish between UC and WB memory so that we can map the page to either a region 6 address (for UC) or a region 7 address (for WB). This change is only now possible, because previously we would map regions 6 and 7 with 256MB translations and on top of that had the kernel mapped in region 7 using a wired translation. The introduction of the PBVM moved the kernel into its own region and freed up region 7 and allowed us to revert to standard page-sized translations. This commit inroduces pmap_page_to_va() that respects the attribute.
* Disable PREEMPTION for now. See also PR ia64/147501.marcel2011-07-041-1/+1
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* With retirement of cpumask_t and usage of cpuset_t for representing aattilio2011-07-041-9/+7
| | | | | | | | | | | | | | | mask of CPUs, pc_other_cpus and pc_cpumask become highly inefficient. Remove them and replace their usage with custom pc_cpuid magic (as, atm, pc_cpumask can be easilly represented by (1 << pc_cpuid) and pc_other_cpus by (all_cpus & ~(1 << pc_cpuid))). This change is not targeted for MFC because of struct pcpu members removal and dependency by cpumask_t retirement. MD review by: marcel, marius, alc Tested by: pluknet MD testing by: marcel, marius, gonzo, andreast
* When iterating over a paging queue, explicitly check for PG_MARKER, insteadalc2011-07-021-1/+1
| | | | | | of relying on zeroed memory being interpreted as an empty PV list. Reviewed by: kib
* Change the management of nested faults by switching to physicalmarcel2011-06-302-133/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | addressing while reading or writing the trap frame. It's not possible to guarantee that the one translation cache entry that we depend on is not going to get purged by the CPU. We already know that global shootdowns (ptc.g and/or ptc.ga) can (and will) cause multiple TC entries to get purged and we initialize tried to handle that by serializing kernel entry with these operations. However, we need to serialize kernel exit as well. But even if we can serialize, it appears that CPU threads within a core can affect each other's TC entries beyond the global shootdown. This would mean serializing any and all translatation cache updates with the threads in a core with the kernel entry and exit of any thread in that core. This is just too painful and complicated. Since we already properly coded for the 2 nested faults that we can get, all we need to do is use those to obtain the physical address of the trap frame, switch to physical mode and in that way eliminate any further faults. The trap frame is already aligned to 1KB boundaries to make sure we don't cross the page boundary, this is safe to do. We still need to serialize ptc.g or ptc.ga across CPUs because the platform can only have 1 such operation outstanding at the same time. We can now use a regular (spin) lock for this. Also, it has been observed that we can get a nested TLB faults for region 7 virtual addresses. This was unexpected. For now, we enhance the nested TLB fault handler to deal with those as well, but it needs to be understood.
* Add a new option, OBJPR_NOTMAPPED, to vm_object_page_remove(). Passing thisalc2011-06-291-2/+2
| | | | | | | | | | | | | | | | | | option to vm_object_page_remove() asserts that the specified range of pages is not mapped, or more precisely that none of these pages have any managed mappings. Thus, vm_object_page_remove() need not call pmap_remove_all() on the pages. This change not only saves time by eliminating pointless calls to pmap_remove_all(), but it also eliminates an inconsistency in the use of pmap_remove_all() versus related functions, like pmap_remove_write(). It eliminates harmless but pointless calls to pmap_remove_all() that were being performed on PG_UNMANAGED pages. Update all of the existing assertions on pmap_remove_all() to reflect this change. Reviewed by: kib
* Oops. The sec field of struct bintime is *not* a 32-bit type.marcel2011-06-251-1/+1
| | | | It's time_t, which is 64 bits on ia64.
* Define the minimum fractional period in terms of hz. We know hz ismarcel2011-06-251-2/+2
| | | | | | | | | a magnitude smaller than itc_freq. A minimum period of 10*hz is sufficient precision. As a side-effect, the number of clocks per second, when the machine is idle, dropped by more than 50%. Be anal and define the maximum period to be at least 4G seconds. With a 64-bit counter and an ITC frequency that's expected to be always less than 4Ghz, it takes longer than that to wrap around.
* Replace the original copyright notice with my own. Everything inmarcel2011-06-251-30/+22
| | | | | this file is written by me and has no bearing on the initial or original version.
* Update copyright.marcel2011-06-251-1/+1
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* Switch to the event timers infrastructure. This includes:marcel2011-06-257-106/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Setting td_intr_frame to the XIVs trap frame because it's referenced by the ET event handler. o Signal EOI to the CPU before calling the registered XIV handlers. This prevents lost ITC interrupts, which cause starvation in one-shot mode. o Adding support for IPI_HARDCLOCK with corresponding per-CPU counters. o Have the APs call cpu_initclocks() so as to limited the scattering of clock related initialization. cpu_initclocks() calls the <self>_bsp() or <self>_ap() version accordingly. o Uncomment the ET clock handling in cpu_idle(). o Update the DDB 'show pcpu' output for the new MD fields. o Entirely rewritten ia64_ih_clock(). Note that we don't create as many clock XIVs as we have CPUs, as is done on PowerPC. It doesn't scale. We can only have 240 XIVs and we can have more CPUs than that. There's a single intrcnt index for the cumulative clock ticks and we keep per CPU counts in the PCPU stats structure. o Register the ITC by hooking SI_SUB_CONFIGURE (2nd order). Open issues: o Clock interrupts can still be lost. Some tweaking is still necessary. Thanks to: mav@ for his support, feedback and explanations. ET stats while committing: eris% sysctl machdep.cpu | grep nclks machdep.cpu.0.nclks: 24007 machdep.cpu.1.nclks: 22895 machdep.cpu.2.nclks: 13523 machdep.cpu.3.nclks: 9342 machdep.cpu.4.nclks: 9103 machdep.cpu.5.nclks: 9298 machdep.cpu.6.nclks: 10039 machdep.cpu.7.nclks: 9479 eris% vmstat -i | grep clock clock 108599 50
* Unblock the outgoing thread after we performed pmap_switch() tomarcel2011-06-231-2/+2
| | | | | | | | | switch the region registers. pmap_switch() returns the pmap for which the region register are currently programmed, which needs to be re-programmed on the CPU the ougoing thread gets switched in. This change does not noticibly change anything or fix known bugs, but does give me a warm fuzzy feeling by being more correct.
* Use a non-standard page size that is supported.alc2011-06-211-1/+1
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* Improve on style(9)marcel2011-06-171-94/+73
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* Properly serialize the global shootdown with the instructionmarcel2011-06-172-2/+15
| | | | | | | stream of the local processor. Also explicitly invalidate the ALAT. This is done on the other CPUs in the coherence domain by virtue of the ptc.ga instruction, but does not apply to the local CPU.
* Add the model number for the Montvale processor (marketed as Itanium 2 9100).marcel2011-06-111-0/+3
| | | | At this time we're missing just one: Tukwila (Itanium 2 9300).
* MFCattilio2011-06-071-0/+2
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| * Call set_cputicker() to have the time counter use the ITC register.marcel2011-06-071-0/+2
| | | | | | | | Note that the ITC frequency is fixed.
* | MFCattilio2011-06-063-18/+47
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| * Improve cpu_idle():marcel2011-06-063-18/+47
| | | | | | | | | | | | | | | | | | | | o cpu_idle_hook is expected to be called with interrupts disabled and re-enables interrupts on return. o sync with x86: don't idle when the CPU has runnable tasks o have callers of ia64_call_pal_static() disable interrupts and re-enable interrupts. o add, but compile-out, support for idle mode. This will be enabled at some later time, after proper testing.
| * On multi-core, multi-threaded PPC systems, it is important that the threadsnwhitehorn2011-05-313-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | be brought up in the order they are enumerated in the device tree (in particular, that thread 0 on each core be brought up first). The SLIST through which we loop to start the CPUs has all of its entries added with SLIST_INSERT_HEAD(), which means it is in reverse order of enumeration and so AP startup would always fail in such situations (causing a machine check or RTAS failure). Fix this by changing the SLIST into an STAILQ, and inserting new CPUs at the end. Reviewed by: jhb
* | MFCattilio2011-05-313-6/+6
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* | MFCattilio2011-05-144-23/+25
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| * Prefer switching the memory stack from user to kernel *before* switchingmarcel2011-05-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | the register stack. While the ordering doesn't matter, it creates an invariant not previously there: the memory stack pointer will always be larger than the register stack pointer. With this invariant in place, it's easier to add instrumentation code that detects a stack overflow because in such a scenario the memory stack pointer and register stack pointers have crossed each other. Aside: basic kernel operation needs about half the stack size (~16K) at most. We have plenty of head room on the kernel stack...
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