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* In pci_cfgregread() and pci_cfgregwrite(), multiplex the domain andmarcel2013-07-231-2/+2
| | | | | | | | | | | | | | | bus number into the bus argument. The bus number occupies the least significant 8 bits. The PCI domain occupies the most significant 24 bits. On the Altix 350, the PCI domain is a required parameter, but changing the prototype of the pci_cfgreg*() functions to include a separate domain argument has wide-spread consequences across the supported architectures. We'd be changing a known interface. Multiplexing is an acceptable kluge to give us what we need with manageable impact. Note that the PCI bus number fits in 8 bits, so the multiplexing of the domain is a backward compatible change.
* Disable interrupts when calling into SAL for PCI configurationmarcel2010-03-221-3/+8
| | | | | | | | cycles. This serves 2 purposes: 1. It prevents preemption and CPU migration while running SAL code. 2. It reduces the chance of stack overflows: we're supposed to enter SAL with at least 16KB of either memory- or register stack space, which we can't do without switching to a different stack.
* In pci_cfgregread() and pci_cfgregwrite(), validate the arguments and checkmarcel2010-01-281-14/+49
| | | | that the alignment matches the width of the read or write.
* Delete legacy pcib code - we can't possibly work without acpi on ia64.dfr2001-10-061-570/+0
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* The encoding for the bus being passed to SAL was completely wrong.dfr2001-10-032-4/+3
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* Start hooking up devices.dfr2001-09-292-0/+635
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