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* If a valid ELCR was found, consult it for the trigger mode of ISAjhb2005-01-182-2/+8
| | | | | | | | | interrupts that have a trigger mode of conforming. This fixes problems on some older machines that still route PCI devices via ISA interrupts when using an I/O APIC. Tested by: Peter Trifonov pvtrifonov at mail dot ru MFC after: 1 month
* Tweak the ELCR support slightly. Explicitly probe the ELCR during bootjhb2005-01-184-12/+6
| | | | | | | | instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
* Unbreak stack traces across double faults. In a particular edge casejhb2005-01-181-2/+8
| | | | | | | | | | | | (calling a __dead2 function such as panic() at the end of a function), the saved %eip on the stack will actually not be part of the function that executed a call instruction but instead will be the first instruction of the next function in the text. This happens with dblfault_handler() and syscall() for example. Work around this in the one place it matters by looking at the saved %eip - 1 to determine the calling function when we check for "magic" frames. MFC after: 2 weeks
* Fix a comment to match reality.ru2005-01-171-1/+1
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* Bah, another whitespace fix.jhb2005-01-141-1/+1
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* Remove an extraneous space.jhb2005-01-141-1/+1
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* Remove redundant code to drop per-thread debug register state fromjhb2005-01-141-7/+1
| | | | | cpu_exit() as this is already performed in cpu_thread_exit() and the debug state is per-thread rather than per-process.
* Drop the 'active-' prefix from the polarity printf to be consistent withjhb2005-01-141-1/+1
| | | | the rest of the interrupt code.
* pcic is no more on i386 port, so remove it from the hints.imp2005-01-141-9/+0
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* Try harder to work with MP table interrupt entries that claim that anjhb2005-01-121-7/+22
| | | | | | | | | | interrupt is wired up to all the I/O APICs in the system. If the system has only one I/O APIC, then just act as if the entry specified that APIC. We still don't try to handle global entries in a system with multiple I/O APICs. Tested by: Peter Trifonov pvtrifonov at mail dot ru MFC after: 1 week
* Fix support for machines with default MP Table configurations:jhb2005-01-071-18/+71
| | | | | | | | | | | | | | | | | | | | | | | | | - Fix the MP Table pci bridge drivers to not probe the configuration table unless we actually have one. Machines using a default configuration do not have such a table. - Only allow default configuration types of 5 (ISA + PCI) and 6 (EISA + PCI) as the others are not likely to work. Types 1 through 4 use an external APIC (probably with 80486 processors) which we certainly do not support, and type 7 uses an MCA bus which has not been tested with the new MP Table code. - Correct the fact that the single I/O APIC in a default configuration has an ID of 2, not 0. - Fix off by one errors in setting the bus types from the default_data[] arrays for default configurations. - Explicitly configure each of the 16 interrupt pins on the sole I/O APIC when using a default configuration. This is especially helpful for type 6 (EISA + PCI) since the EISA interrupts need to have their polarity programmed based on the values in the ELCR. Much thanks to the submitter and tester who endured several rounds of testing to get this fixed. MFC after: 1 week Tested by: Georg Schwarz georg dot schwarz at freenet dot de
* Introduce bus_dmamap_load_mbuf_sg(). Instead of taking a callback arg, thisscottl2005-01-072-13/+53
| | | | | | | cuts to the chase and fills in a provided s/g list. This is meant to optimize out the cost of the callback since the callback doesn't serve much purpose for mbufs since mbuf loads will never be deferred. This is just for amd64 and i386 at the moment, other arches will be coming shortly.
* These are no longer relevant. They are scripts for extracting hintsimp2005-01-071-116/+0
| | | | | | from 4.x kernel config files. User's wishing to upgrade from 4.x to 6 will need to go through 5.x, or grab this script from there. These scripts will remain in RELENG_5...
* This is no longer supported, so remove it from the tree.imp2005-01-071-17/+0
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* /* -> /*- for license, add FreeBSD tagimp2005-01-0631-32/+48
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* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-0667-81/+90
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* Remove left over include file from stallion driver.imp2005-01-061-122/+0
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* Expand indirect reference to BSD license with the current one.imp2005-01-061-2/+22
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* This doesn't seem to have been used since 386BSD daysimp2005-01-061-4/+0
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* - Move the function prototypes for kern_setrlimit() and kern_wait() tojhb2005-01-051-0/+1
| | | | | sys/syscallsubr.h where all the other kern_foo() prototypes live. - Resort kern_execve() while I'm there.
* These appear to be unused in our tree, so remove them.imp2005-01-051-45/+0
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* Start all license/copyright notice comments with /*-, per traditionimp2005-01-059-9/+9
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* o Use tab instead of spaces for puc(4) line.kuriyama2005-01-051-4/+4
| | | | o Use capitalized "Ethernet" for consistency.
* Use NULL instead of 0 in a few places as well as various whitespace fixes.jhb2004-12-302-12/+12
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* Small whitespace fixes.jhb2004-12-301-2/+1
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* - Indent the comments beside the SMP options to the same level as all thejhb2004-12-301-4/+4
| | | | | | | other comments. Clarify that the next two things needed for SMP are two lines. - Expand mii abbreviation to miibus for clarity in the USB ethernet comment.
* Restore the cpu_reset proxy code. It is needed if you want to reset thenjl2004-12-271-1/+41
| | | | | | | system from an AP at runtime (i.e., calling cpu_reset from ddb). Someday, if we move to an NMI for stopping cpus instead, we can do away with this. Requested by: jhb
* Get rid of #ifdef for legacy system. Move that into the MD code.imp2004-12-241-0/+7
| | | | Export minimal symbols to allow this to happen.
* - Give the timer, thermal, and error LVT entries an interrupt vector evenjhb2004-12-231-22/+30
| | | | | | | | | | | | | | though these aren't used yet. - Add missing function prototypes for some static functions. - Allow lvt_mode() to handle an LVT entry with a delivery mode of fixed. - Consolidate code duplicated in lapic_init() and lapic_setup() to program the spurious vector register of a local APIC in a static lapic_enable() function. - Dump the timer, thermal, error, and performance counter LVT entries during lapic_dump(). - Program LVT pins (currently only LINT0 and LINT1) after the local APIC has been software enabled via lapic_enable() since otherwise the LVT programming will not be able to unmask LVT sources.
* Some small style fixes.jhb2004-12-231-3/+2
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* Add some constants for the local APIC timer.jhb2004-12-231-0/+5
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* Add a simple 'intrcnt_add' function that other MD code can use to add ajhb2004-12-232-0/+12
| | | | | single named counter to the interrupt counts without having to fake up an entire interrupt source.
* Modify pmap_enter_quick() so that it expects the page queues to be lockedalc2004-12-231-3/+2
| | | | | | | | | | | on entry and it assumes the responsibility for releasing the page queues lock if it must sleep. Remove a bogus comment from pmap_enter_quick(). Using the first change, modify vm_map_pmap_enter() so that the page queues lock is acquired and released once, rather than each time that a page is mapped.
* - Add a function to set the Task Priority Register (TPR) of the local APIC.jhb2004-12-232-18/+39
| | | | | | | | | | | | | | | Currently this is only used to initiailize the TPR to 0 during initial setup. - Reallocate vectors for the local APIC timer, error, and thermal LVT entries. The timer entry is allocated from the top of the I/O interrupt range reducing the number of vectors available for hardware interrupts to 191. Linux happens to use the same exact vector for its timer interrupt as well. If the timer vector shared the same priority queue as the IPI handlers, then the frequency that the timer vector will eventually be firing at can interact badly with the IPIs resulting in the queue filling and the dreaded IPI stuck panics, hence it being located at the top of the previous priority queue instead. - Fixup various minor nits in comments.
* In the common case, pmap_enter_quick() completes without sleeping.alc2004-12-151-2/+12
| | | | | | | | | | | | | | | | | | In such cases, the busying of the page and the unlocking of the containing object by vm_map_pmap_enter() and vm_fault_prefault() is unnecessary overhead. To eliminate this overhead, this change modifies pmap_enter_quick() so that it expects the object to be locked on entry and it assumes the responsibility for busying the page and unlocking the object if it must sleep. Note: alpha, amd64, i386 and ia64 are the only implementations optimized by this change; arm, powerpc, and sparc64 still conservatively busy the page and unlock the object within every pmap_enter_quick() call. Additionally, this change is the first case where we synchronize access to the page's PG_BUSY flag and busy field using the containing object's lock rather than the global page queues lock. (Modifications to the page's PG_BUSY flag and busy field have asserted both locks for several weeks, enabling an incremental transition.)
* Remove a stray critical_exit().scottl2004-12-131-1/+0
| | | | Submitted by: johan
* Separate mse driver into a core driver and a bus attachments. Separate outimp2004-12-121-917/+0
| | | | | | | | | | | | | the ISA and CBUS (called isa on pc98) attachments. Eliminate all PC98 ifdefs in the process (the driver in pc98/pc98/mse.c was a copy of the one in i386/isa/mse.c with PC98 ifdefs). Create a module for this driver. I've tested this my PC-9821RaS40 with moused. I've not tested this on i386 because I have no InPort cards, or similar such things. NEC standardized on bus mice very early, long before ps/2 mice ports apeared, so all PC-98 machines supported by FreeBSD/pc98 have bus mice, I believe. Reviewed by: nyan-san
* Only export defined symbols. Note that I couldn't find any differencenjl2004-12-121-1/+1
| | | | | | | | between object code generated without the flag but it makes sense and might make a difference in the future. PR: kern/53008 Submitted by: Jens Rehsack rehsack at liwing de
* Move the author's copyright notice to match the initial LongRun importnjl2004-12-122-2/+1
| | | | now that we have split out this support into longrun.c
* Expand the scope of the critical section in the PCIe read and write methodsscottl2004-12-101-4/+14
| | | | on the advice of Alan Cox.
* If the parent process has the trap bit set (i.e. a debugger had singlekbyanc2004-12-081-0/+12
| | | | | | | | | | stepped the process to the system call), we need to clear the trap flag from the new frame unless the debugger had set PF_FORK on the parent. Otherwise, the child will receive a (likely unexpected) SIGTRAP when it executes the first instruction after returning to userland. Reviewed by: bde MFC after: 3 days
* add ath rate control module(s)sam2004-12-081-0/+2
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* Avoid more than two pending IPI interrupt vectors per local APICups2004-12-074-103/+114
| | | | | | | | | | | as this may cause deadlocks. This should fix kern/72123. Discussed with: jhb Tested by: Nik Azim Azam, Andy Farkas, Flack Man, Aykut KARA Izzet BESKARDES, Jens Binnewies, Karl Keusgen Approved by: sam (mentor)
* NEC PC-98 machines do not have and cannot have an EISA bus. They haveimp2004-12-071-0/+2
| | | | | | | only C-Bus and PCI busses. Therefore, don't create an eisa0 node on the legacy bus that can never attach. PC-98 info verified by: nyan-san
* PNP BIOS devices are fundamentally different than ISA PNP devices.imp2004-12-071-1/+1
| | | | | | | These devices should be probed first because they are at fixed locations and cannot be turned off. ISA PNP devices, on the other hand, can be turned off and often can be flexible in the resources they use. Probe them last, as always.
* Move reading the current CPU mask in pmap_lazyfix() to where the threadups2004-12-071-1/+2
| | | | | | | is protected from migrating to another CPU. Approved by: sam (mentor) MFC after: 4 weeks
* Allow fast interrupts to cause preemption.ups2004-12-061-2/+0
| | | | | Reviewed by: jhb, scottl Approved by: sam (mentor)
* Due to a significant addition of code, add my copyright to this file. Alsoscottl2004-12-061-0/+1
| | | | | note that the PCIe work was made possible due to hardware donations from the FreeBSD Foundation and Intel. Thanks!
* Add support for the memory-mapped PCI Express configuration mechanism. Thisscottl2004-12-061-8/+211
| | | | | | | | | | | | | | actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe devices in the system, though only PCIe devices will respond to registers higher than 256. This uses per-CPU pools of temporary mappings so that the whole 256MB of configuration space doesn't have to be mapped all at once. While the sf_buf API was considered for this, the fact that it requires sleep locks and can return failure made it unsuitable for this use. For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are supported. Since there doesn't appear to be a compatible way to determine northbridge support, new chipsets will have to be explicitely added in the future.
* Enable amr(4) - scottl fixed when used with >4GB RAM.obrien2004-12-061-1/+0
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