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* - Create a separate section in in the MI NOTES file for PCI wireless NICjhb2009-12-181-19/+0
| | | | | | | drivers and move bwi(4) there from the PCI Ethernet NIC section. - Move ath(4) and ral(4) to the MI NOTES file. Reviewed by: rpaulo
* Add INCLUDE_CONFIG_FILE, and a note in comments about how to alsodougb2009-12-161-0/+7
| | | | include the comments with CONFIGARGS
* Remove comment claiming that building acpi into the kernel is deprecated.jhb2009-12-141-3/+0
| | | | | | PR: docs/141353 Submitted by: Bruce Cran MFC after: 1 week
* for PV XEN translate page table entries from machine (real) to physical ↵kmacy2009-12-101-0/+16
| | | | | | (logical) addresses so that kgdb can translate them to the correct coredump offsets
* - revert pmap_kenter_temporary to taking a physical addresskmacy2009-12-103-9/+11
| | | | - make minidump work
* make PV core dump actually dump memory - still need to fix program header ↵kmacy2009-12-092-0/+7
| | | | initialization
* mca: small enhancements related to cpu quirksavg2009-12-031-8/+22
| | | | | | | | | | | | - use utility macros for CPU family/model checking - limit Intel P6 quirk to pre-Nehalem models (taken from OpenSolaris) - add AMD GartTblWkEn quirk for families 0Fh and 10h; I haven't experienced any problems without the quirk but both Linux and OpenSolaris do this - slightly re-arrange quirk code to provide for the future generalization and separation of vendor-specific quirk functions Reviewed by: jhb MFC after: 1 week
* Fix cut'n paste on the AR9280 entry.thompsa2009-12-021-1/+1
| | | | Submitted by: pluknet
* mca: improve status checking, recording and reportingavg2009-12-022-49/+63
| | | | | | | | | | - directly print mca information in case we fail to allocate memory for a record - include bank number into mca record - print raw mca status value for extended information Reviewed by: jhb MFC after: 10 days
* Add missing ath_ar9* ath hal entries.thompsa2009-12-021-0/+2
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* amdsbwd: new driver for AMD SB600/SB7xx watchdog timeravg2009-11-301-0/+2
| | | | | | | | | | | | The hardware is compliant with WDRT specification, so I originally considered including generic WDRT watchdog support, but decided against it, because I couldn't find anyone to the code for me. WDRT seems to be not very popular. Besides, generic WDRT porbably requires a slightly different driver approach. Reviewed by: des, gavin, rpaulo MFC after: 3 weeks
* x86 cpu features: add MOVBE reporting and flagavg2009-11-302-1/+2
| | | | | The check is glimpsed from Linux and OpenSolaris. MOVBE instruction is found in Intel Atom processors.
* Simplify the invocation of vm_fault(). Specifically, eliminate the flagalc2009-11-271-3/+1
| | | | | | | VM_FAULT_DIRTY. The information provided by this flag can be trivially inferred by vm_fault(). Discussed with: kib
* i386 has not (yet) any DEV_ATPIC conditional than axe it out from Xenattilio2009-11-271-4/+0
| | | | | | version. No objections by: kmacy
* fixup kernel core dumps on paravirtual guestskmacy2009-11-241-1/+1
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* - Add more aggressive BPF JIT optimization. This is in more favor of i386jkim2009-11-232-58/+105
| | | | | | | while the previous commit was more amd64-centric. - Use calloc(3) instead of malloc(3)/memset(3) in user land[1]. Submitted by: ed[1]
* Add an experimental and rudimentary JIT optimizer to reduce unncessaryjkim2009-11-212-47/+127
| | | | overhead from short BPF filter programs such as "get the first 96 bytes".
* General style cleanup, no functional change.jkim2009-11-201-32/+29
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* - Allocate scratch memory on stack instead of pre-allocating it withjkim2009-11-202-17/+27
| | | | | | | | | the filter as we do from bpf_filter()[1]. - Revert experimental use of contigmalloc(9)/contigfree(9). It has no performance benefit over malloc(9)/free(9)[2]. Requested by: rwatson[1] Pointed out by: rwatson, jhb, alc[2]
* Fix tinderbox build for i386 and sync amd64 with it.jkim2009-11-191-1/+1
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* - Change internal function bpf_jit_compile() to return allocated size ofjkim2009-11-181-9/+7
| | | | | | the generated binary and remove page size limitation for userland. - Use contigmalloc(9)/contigfree(9) instead of malloc(9)/free(9) to make sure the generated binary aligns properly and make it physically contiguous.
* - Make BPF JIT compiler working again in userland. We are limiting size ofjkim2009-11-182-12/+25
| | | | | generated native binary to page size for now. - Update copyright date and fix some style nits.
* Previous solution appeared to be unsufficient. After additional testingmav2009-11-141-18/+18
| | | | | | | | | | | | | I have found that it is not only desktop CPUs problem. but mobile also. Probably AP on laptops just started initially at lower frequency, hiding the problem. Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it. Now my iXsystems Invincibook is able to run at 800MHz lowest frequency, instead of 1200MHz before, when 800MHz was incorrectly reported invalid.
* Retry only once, if BIOS is completely broken and gives zero freqs.mav2009-11-141-1/+1
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* Desktop Core2Duo/Core2Quad CPUs are unable to control frequency of singlemav2009-11-141-3/+12
| | | | | | | | | | | CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable. To workaround this, add check for validation result. If we haven't found at least two usable frequencies, then probably we are looking bad and have to trust data provided by BIOS as-is.
* Fix cpu model for PODP5V83. It is P24T, not P54T.nyan2009-11-121-1/+1
| | | | | | | Also remove redundant 'Overdrive' word. Pointed out by: SATOU Tomokazu (tomo1770 at maple ocn ne jp) MFC after: 1 week
* - Style nits.kuriyama2009-11-121-3/+1
| | | | | | - Remove unneeded TUNABLE_INT(). Suggested by: avg, kib
* reflect that pg_ps_enabled is a tunable, not just a read-only sysctlavg2009-11-112-2/+2
| | | | Nod from: jhb
* Extract the code that records syscall results in the frame into MDkib2009-11-102-29/+37
| | | | | | | | | | | function cpu_set_syscall_retval(). Suggested by: marcel Reviewed by: marcel, davidxu PowerPC, ARM, ia64 changes: marcel Sparc64 tested and reviewed by: marius, also sunv reviewed MIPS tested by: gonzo MFC after: 1 month
* Make isa_dma functions MPSAFE by introducing its own private lock. Theserdivacky2009-11-091-27/+83
| | | | | | | | | | | | | | | | | | functions are selfcontained (ie. they touch only isa_dma.c static variables and hardware) so a private lock is sufficient to prevent races. This changes only i386/amd64 while there are also isa_dma functions for ia64/sparc64. Sparc64 are ones empty stubs and ia64 ones are unused as ia64 does not have isa (says marcel). This patch removes explicit locking of Giant from a few drivers (there are some that requires this but lack ones - this patch fixes this) and also removes the need for implicit locking of Giant from attach routines where it's provided by newbus. Approved by: ed (mentor, implicit) Reviewed by: jhb, attilio (glanced by) Tested by: Giovanni Trematerra <giovanni.trematerra gmail com> IA64 clue: marcel
* - Add hw.clflush_disable loader tunable to avoid panic (trap 9) atkuriyama2009-11-091-1/+18
| | | | | | | | | | | | | | map_invalidate_cache_range() even if CPU is not Intel. - This tunable can be set to -1 (default), 0 and 1. -1 is same as current behavior, which automatically disable CLFLUSH on Intel CPUs without CPUID_SS (should be occured on Xen only). You can specify 1 when this panic happened on non-Intel CPUs (such as AMD's). Because disabling CLFLUSH may reduce performance, you can try with setting 0 on Intel CPUs without SS to use CLFLUSH feature. Reviewed by: kib Reported by: karl, kuriyama Related to: kern/138863
* Strip from messages for users external URLs the project cannot directlyattilio2009-11-051-4/+1
| | | | | | control. Requested by: kib, rwatson
* Opteron rev E family of processor expose a bug where, in very rareattilio2009-11-041-0/+18
| | | | | | | | | | | | | | | | ocassions, memory barriers semantic is not honoured by the hardware itself. As a result, some random breakage can happen in uninvestigable ways (for further explanation see at the content of the commit itself). As long as just a specific familly is bugged of an entire architecture is broken, a complete fix-up is impratical without harming to some extents the other correct cases. Considering that (and considering the frequency of the bug exposure) just print out a warning message if the affected machine is identified. Pointed out by: Samy Al Bahra <sbahra at repnop dot org> Help on wordings by: jeff MFC: 3 days
* Unobfuscate unit number handling in apm(4).ed2009-10-311-13/+9
| | | | | | | | There is no need to use the lower 4 bits of the unit number to store the device type number. Just use 0 and 1 to distinguish them. devfs also guarantees that there can never be an open call on a device that has a unit number different to 0 and 1, so there is no need to check for this in open().
* Fix some problems with effective mmap() offsets > 32 bits. This wasjhb2009-10-281-34/+31
| | | | | | | | | | | | partially fixed on amd64 earlier. Rather than forcing linux_mmap_common() to use a 32-bit offset, have it accept a 64-bit file offset. This offset is then passed to the real mmap() call. Rather than inventing a structure to hold the normal linux_mmap args that has a 64-bit offset, just pass each of the arguments individually to linux_mmap_common() since that more closes matches the existing style of various kern_foo() functions. Submitted by: Christian Zander @ Nvidia MFC after: 1 week
* In r197963, a race with thread being selected for signal deliverykib2009-10-272-33/+12
| | | | | | | | | | | | | while in kernel mode, and later changing signal mask to block the signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls. Use kern_sigprocmask() instead of direct manipulation of td_sigmask to reschedule newly blocked signals, closing the race. Reviewed by: davidxu Tested by: pho MFC after: 1 month
* o Introduce vm_sync_icache() for making the I-cache coherent withmarcel2009-10-212-0/+10
| | | | | | | | | | | | | | | | | | | | | the memory or D-cache, depending on the semantics of the platform. vm_sync_icache() is basically a wrapper around pmap_sync_icache(), that translates the vm_map_t argumument to pmap_t. o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc it replaces the pmap_page_executable() function, added to solve the I-cache problem in uiomove_fromphys(). o In proc_rwmem() call vm_sync_icache() when writing to a page that has execute permissions. This assures that when breakpoints are written, the I-cache will be coherent and the process will actually hit the breakpoint. o This also fixes the Book-E PMAP implementation that was missing necessary locking while trying to deal with the I-cache coherency in pmap_enter() (read: mmu_booke_enter_locked). The key property of this change is that the I-cache is made coherent *after* writes have been done. Doing it in the PMAP layer when adding or changing a mapping means that the I-cache is made coherent *before* any writes happen. The difference is key when the I-cache prefetches.
* add amdtemp to i386 NOTESavg2009-10-201-0/+2
| | | | | | essentially this is a MFamd64 Nod from: rpaulo
* Move intr_describe() out of #ifdef SMP; the function is always required.kib2009-10-161-17/+17
| | | | Reviewed by: jhb
* Add a facility for associating optional descriptions with active interruptjhb2009-10-153-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | handlers. This is primarily intended as a way to allow devices that use multiple interrupts (e.g. MSI) to meaningfully distinguish the various interrupt handlers. - Add a new BUS_DESCRIBE_INTR() method to the bus interface to associate a description with an active interrupt handler setup by BUS_SETUP_INTR. It has a default method (bus_generic_describe_intr()) which simply passes the request up to the parent device. - Add a bus_describe_intr() wrapper around BUS_DESCRIBE_INTR() that supports printf(9) style formatting using var args. - Reserve MAXCOMLEN bytes in the intr_handler structure to hold the name of an interrupt handler and copy the name passed to intr_event_add_handler() into that buffer instead of just saving the pointer to the name. - Add a new intr_event_describe_handler() which appends a description string to an interrupt handler's name. - Implement support for interrupt descriptions on amd64 and i386 by having the nexus(4) driver supply a custom bus_describe_intr method that invokes a new intr_describe() MD routine which in turn looks up the associated interrupt event and invokes intr_event_describe_handler(). Requested by: many Reviewed by: scottl MFC after: 2 weeks
* Move the USB wireless drivers down into their own section next to the USBjhb2009-10-131-4/+5
| | | | | | | ethernet drivers. Submitted by: Glen Barber glen.j.barber @ gmail MFC after: 1 month
* Define architectural load bases for PIE binaries. Addresses were selectedkib2009-10-101-0/+2
| | | | | | | | | | by looking at the bases used for non-relocatable executables by gnu ld(1), and adjusting it slightly. Discussed with: bz Reviewed by: kan Tested by: bz (i386, amd64), bsam (linux) MFC after: some time
* atomic_cmpset_barr_* was added in order to cope with compilers willing toattilio2009-10-091-64/+48
| | | | | | | | | | | | | | | | | specify their own version of atomic_cmpset_* which could have been different than the membar version. Right now, however, FreeBSD is bound mostly to GCC-like compilers and it is desired to add new support and compat shim mostly when there is a real necessity, in order to avoid too much compatibility bloats. In this optic, bring back atomic_cmpset_{acq, rel}_* to be the same as atomic_cmpset_* and unwind the atomic_cmpset_barr_* introduction. Requested by: jhb Reviewed by: jhb Tested by: Giovanni Trematerra <giovanni dot trematerra at gmail dot com>
* - All the functions in atomic.h needs to be in "physical" form (likeattilio2009-10-061-45/+50
| | | | | | | | | | | | not defined through macros or similar) in order to be later compiled in the kernel and offer this way the support for modules (and compatibility among the UP case and SMP case). Fix this for the newly introduced atomic_cmpset_barr_* cases by defining and specifying a template. Note that the new DEFINE_CMPSET_GEN() template save more typing on amd64 than the current code. [1] - Fix the style for memory barriers on amd64. [1] Reported by: Paul B. Mahol <onemda at gmail dot com>
* Per their definition, atomic instructions used in conjuction withattilio2009-10-061-46/+73
| | | | | | | | | | | | | | | | | | | | | | | | memory barriers should also ensure that the compiler doesn't reorder paths where they are used. GCC, however, does that aggressively, even in presence of volatile operands. The most reliable way GCC offers for avoid instructions reordering is clobbering "memory" even if that is theoretically an heavy-weight operation, flushing the content of all the registers and forcing reload of them (We could rely, however, on gcc DTRT by just understanding the purpose as this is a well-known pattern for many modern operating-systems). Not all our memory barriers, right now, clobber memory for GCC-like compilers. The most notable cases are IA32 and amd64 where the memory barrier are treacted the same as normal atomic instructions. Fix this by offering the possibility to implement atomic instructions with memory barriers separately from the normal version and implement the GCC-like specific one using memory clobbering. Thanks to Chris Lattner (@apple) for his discussion on llvm specifics. Reported by: jhb Reviewed by: jhb Tested by: rdivacky, Giovanni Trematerra <giovanni dot trematerra at gmail dot com>
* Make sure that the primary native brandinfo always gets addedbz2009-10-031-1/+1
| | | | | | | | | | | | | first and the native ia32 compat as middle (before other things). o(ld)brandinfo as well as third party like linux, kfreebsd, etc. stays on SI_ORDER_ANY coming last. The reason for this is only to make sure that even in case we would overflow the MAX_BRANDS sized array, the native FreeBSD brandinfo would still be there and the system would be operational. Reviewed by: kib MFC after: 1 month
* make read_eflags and write_eflags accomplish the same effect on PVM as native,kmacy2009-10-013-28/+42
| | | | simplifying interrupt handling
* As a workaround, for Intel CPUs, do not use CLFLUSH inkib2009-10-011-0/+6
| | | | | | | | | | | | | pmap_invalidate_cache_range() when self-snoop is apparently not reported in cpu features. We get a reserved trap when clflushing APIC registers window. XEN in full system virtualization mode removes self-snoop from CPU features, making this a problem. Tested by: csjp Reviewed by: alc MFC after: 3 days
* Improve 802.11s comment.rpaulo2009-10-011-1/+1
| | | | | Spotted by: dougb MFC after: 1 day
* cpufunc.h: unify/correct style of c extension namesavg2009-09-301-2/+2
| | | | | | | | | | i386 and amd64 archs only. inline => __inline. [1] __asm__ => __asm. [2] Reviewed by: kib, jhb [1] Suggested by: kib [2] MFC after: 1 week
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