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* - Create a pir0 psuedo device as a child of legacy0 if we attach a legacyjhb2004-05-042-8/+125
* Make the legacy_pcib_attach() function static.jhb2004-05-031-1/+1
* Don't call the BIOS to route a link that has already been routed by thejhb2004-04-161-2/+3
* Add back an include to fix the build for the CPU_ELAN case.jhb2004-02-191-0/+3
* Switch to using the new $PIR interrupt routing code and remove the oldjhb2004-02-182-434/+17
* Rework the $PIR (aka PCIBIOS) PCI interrupt routing code and split it offjhb2004-02-181-609/+445
* Replace an outb() during the test for configuration mechanism #1 with ajhb2003-12-312-2/+2
* New APIC support code:jhb2003-11-032-98/+4
* Lower the priority of the legacy host to pci bridge driver so that otherjhb2003-10-311-1/+1
* Change all SYSCTLS which are readonly and have a related TUNABLEsilby2003-10-212-2/+2
* We represent PCI intpin's two different ways. One is the way that thejhb2003-09-102-2/+2
* - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.jhb2003-08-281-3/+3
* Prefer new location of pci include files (which have only been in theimp2003-08-221-3/+3
* PC98 uses different mask of IRQ.nyan2003-08-022-4/+16
* The MI code was modified to filter the devices based on its headerimp2003-08-011-0/+8
* Add hw.pci.irq_override_mask, which is a mask of interrupts that areimp2003-08-012-0/+28
* - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for ajhb2003-06-061-56/+50
* Use the secondary bus number instead of the number of the bus the PCI-PCIjhb2003-06-061-1/+5
* Use __FBSDID().obrien2003-06-023-9/+9
* Remove unused variable.phk2003-05-311-2/+1
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-183-276/+56
* Outdent the string rather than use concatenation.phk2002-12-231-2/+2
* MFp4:imp2002-11-142-2/+2
* Recognize the Serverworks CIOB30 host to pci bridge.peter2002-11-131-0/+5
* MFp4:imp2002-11-022-20/+68
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-022-20/+22
* Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread().phk2002-10-201-0/+2
* "id" is never going to be -1 when it is unsigned.phk2002-10-201-2/+0
* Use the global pcib devclass instead of our own static copy.jhb2002-10-161-2/+0
* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-072-14/+24
* Add 2 Ids for new ServerWorks host to PCI bridge chipset.iwasaki2002-10-021-0/+8
* Don't call function in return() for a void function.phk2002-09-282-6/+10
* Now that we only probe host-PCI bridges once, we no longer have to check tojhb2002-09-231-10/+0
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-232-2/+8
* Change the nexus_pcib driver (eventually to be renamed to legacy_pcib) tojhb2002-09-231-7/+7
* Axe unused include.jhb2002-09-202-2/+0
* Make sure a $PIR table header has a valid length before accepting the tablejhb2002-09-092-2/+4
* #include "opt_bla.h" goes first says Bruce.phk2002-09-091-2/+2
* Fix style(9) bugs.phk2002-09-081-2/+2
* Add a subclass of the PCI-PCI bridge driver that uses the PCIBIOS tojhb2002-09-061-2/+69
* Add a function pci_probe_route_table() that returns true if our PCI BIOSjhb2002-09-062-0/+38
* Dump the $PIR table if booting verbose.jhb2002-09-062-0/+6
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validjhb2002-09-063-3/+68
* Add support for printing out the contents of a PCI BIOS $PIR interruptjhb2002-09-062-4/+108
* Prefer the physical bus number of the PCI bus as the unit of the pciXjhb2002-09-061-1/+1
* Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,jhb2002-09-052-4/+4
* Change the support for AMDs ElanSC520 CPU from being a device driver tophk2002-09-041-0/+7
* Move a prototype to the least wrong place.phk2002-08-021-0/+1
* style(9)ize the whole fileimp2002-07-212-948/+984
* Add support for probing secondary buses on the ServerWorks Grand Championgallatin2002-07-191-0/+11
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