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* Make a bunch of malloc types static.phk2005-02-101-1/+1
| | | | Found by: src/tools/tools/kernxref
* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-063-3/+3
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* Remove a stray critical_exit().scottl2004-12-131-1/+0
| | | | Submitted by: johan
* Expand the scope of the critical section in the PCIe read and write methodsscottl2004-12-101-4/+14
| | | | on the advice of Alan Cox.
* Due to a significant addition of code, add my copyright to this file. Alsoscottl2004-12-061-0/+1
| | | | | note that the PCIe work was made possible due to hardware donations from the FreeBSD Foundation and Intel. Thanks!
* Add support for the memory-mapped PCI Express configuration mechanism. Thisscottl2004-12-061-8/+211
| | | | | | | | | | | | | | actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe devices in the system, though only PCIe devices will respond to registers higher than 256. This uses per-CPU pools of temporary mappings so that the whole 256MB of configuration space doesn't have to be mapped all at once. While the sf_buf API was considered for this, the fact that it requires sleep locks and can return failure made it unsuitable for this use. For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are supported. Since there doesn't appear to be a compatible way to determine northbridge support, new chipsets will have to be explicitely added in the future.
* Add TUNABLE_LONG and TUNABLE_ULONG, and use the latter for thedes2004-10-311-4/+3
| | | | | | | hw.pci.host_mem_start tunable. Add comments to TUNABLE_INT and TUNABLE_QUAD recommending against their use. MFC after: 3 weeks
* Whitespace cleanupdes2004-10-311-8/+8
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* Make the lower range of the memory area 0x80000000 again. Alsoimp2004-10-111-1/+15
| | | | | | introduce hw.{pci,acpi}.host_mem_start tunable to change this. MFC: ASAP
* Add missing 'static'imp2004-10-061-2/+1
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* For legacy PCI bridges, limit memory allocation to the top 32MB ofimp2004-10-061-4/+24
| | | | | | | | | | | RAM. Many older, legacy bridges only allow allocation from this range. This only appies to devices who don't have their memory assigned by the BIOS (since we allocate the ranges so assigned exactly), so should have minimal impact. Hoewver, for CardBus bridges (cbb), they rarely get the resources allocated by the BIOS, and this patch helps them greatly. Typically the 'bad Vcc' messages are caused by this problem.
* Consistently use __inline instead of __inline__ as the former is an empty macrostefanf2004-07-041-1/+1
| | | | in <sys/cdefs.h> for compilers without support for inline.
* Trim a few things from the dmesg output and stick them under bootverbose tojhb2004-07-012-4/+5
| | | | | | | cut down on the clutter including PCI interrupt routing, MTRR, pcibios, etc. Discussed with: USENIX Cabal
* Remove atdevbase and replace it's remaining uses with direct references tojhb2004-06-101-0/+1
| | | | KERNBASE instead.
* Allow the pir0 device add to fail since pir0 may already exist. This shouldjhb2004-06-011-2/+2
| | | | | fix the panics in device_set_ivars() that people were seeing on boxes with multiple Host-PCI bridges but not using ACPI.
* Add some missing <sys/module.h> includes which are masked by thephk2004-05-302-0/+2
| | | | one on death-row in <sys/kernel.h>
* - Create a pir0 psuedo device as a child of legacy0 if we attach a legacyjhb2004-05-042-8/+125
| | | | | | | | | | | | | | | | | host-PCI bridge device and find a valid $PIR. - Make pci_pir_parse() private to pci_pir.c and have pir0's attach routine call it instead of having legacy_pcib_attach() call it. - Implement suspend/resume support for the $PIR by giving pir0 a resume method that calls the BIOS to reroute each link that was already routed before the machine was suspended. - Dump the state of the routed flag in the links display code. - If a link's IRQ is set by a tunable, then force that link to be re-routed the first time it is used. - Move the 'Found $PIR' message under bootverbose as the pir0 description line lists the number of entries already. The pir0 line also only shows up if we are actually using the $PIR which is a bonus. - Use BUS_CONFIG_INTR() to ensure that any IRQs used by a PCI link are set to level/low trigger/polarity.
* Make the legacy_pcib_attach() function static.jhb2004-05-031-1/+1
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* Don't call the BIOS to route a link that has already been routed by thejhb2004-04-161-2/+3
| | | | | | BIOS during POST as it apparently makes some machines unhappy. Tested by: mux
* Add back an include to fix the build for the CPU_ELAN case.jhb2004-02-191-0/+3
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* Switch to using the new $PIR interrupt routing code and remove the oldjhb2004-02-182-434/+17
| | | | | code. The pci_cfgreg.c file now just controls reading/writing PCI config registers.
* Rework the $PIR (aka PCIBIOS) PCI interrupt routing code and split it offjhb2004-02-181-609/+445
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into its own file: - All of the $PIR interrupt routing is now done in a link-centric fashion. When a host-PCI bridge that uses the $PIR attaches, it calls pir_parse() to parse the table. This scans for link devices and merges all the masks for each link device from the table entries. It then looks at the intline register of PCI devices connected to a link to figure out if the BIOS has routed this link and if so to which IRQ. - The IRQ for any given link can be overridden via a hint like so: 'hw.pci.link.0x62.irq=10' Any IRQ set in this matter is treated as if it were set that way by the BIOS. - We only call the BIOS to route each link device once. - When a PCI device wants to route an interrupt, we look it up in the $PIR to find the associated link. If the link is routed, we simply return the IRQ it is using. If it is not routed, we have to pick one. This uses a different algorithm from the old code. First off, when we try to pick an interrupt from a mask of possible interrupts, we try to pick the one that is least loaded as far as PCI devices. We maintain this weight based on the number of devices attached to each link device. When choosing an IRQ, we first attempt to route using any PCI only interrupts (the old code did this as well). If that doesn't work, we try to use the list of IRQs that the BIOS has used. This is a new step that the new code didn't do and avoids using IRQ 3 or 4 for every virgin interrupt routing. If none of the IRQs that the BIOS used worked, then we fall back to trying anything. - The fallback mask for !PC98 was fixed to include IRQ 3 and not allow IRQ 2. - We don't use the $PIR to route interrupts on a PCI-PCI bridge unless it has already been used to route on at least one Host-PCI bridge. This helps to avoid mixing and matching x86 firmware PCI interrupt routing methods (which is a Bad Thing(tm)). Silence on: current@
* Replace an outb() during the test for configuration mechanism #1 with ajhb2003-12-312-2/+2
| | | | | | | | | | | | | DELAY(1) instead. After wading through old commit logs, I found that the outb() was added not as part of the test but as an intentional delay. In fact, according to Shanley's PCI book, the configuration 1 data and address ports should only be accessed using aligned 32-bit accesses (i.e. inl() and outl()). Thus, using outb() to just the last byte of the port violates the PCI spec it would seem. On at least one box doing so broke the probe for PCI, whereas changing it to a DELAY(1) fixed the probe. Reported by: Sean Welch <welchsm@earthlink.net> MFC after: 1 week
* New APIC support code:jhb2003-11-032-98/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The apic interrupt entry points have been rewritten so that each entry point can serve 32 different vectors. When the entry is executed, it uses one of the 32-bit ISR registers to determine which vector in its assigned range was triggered. Thus, the apic code can support 159 different interrupt vectors with only 5 entry points. - We now always to disable the local APIC to work around an errata in certain PPros and then re-enable it again if we decide to use the APICs to route interrupts. - We no longer map IO APICs or local APICs using special page table entries. Instead, we just use pmap_mapdev(). We also no longer export the virtual address of the local APIC as a global symbol to the rest of the system, but only in local_apic.c. To aid this, the APIC ID of each CPU is exported as a per-CPU variable. - Interrupt sources are provided for each intpin on each IO APIC. Currently, each source is given a unique interrupt vector meaning that PCI interrupts are not shared on most machines with an I/O APIC. That mapping for interrupt sources to interrupt vectors is up to the APIC enumerator driver however. - We no longer probe to see if we need to use mixed mode to route IRQ 0, instead we always use mixed mode to route IRQ 0 for now. This can be disabled via the 'NO_MIXED_MODE' kernel option. - The npx(4) driver now always probes to see if a built-in FPU is present since this test can now be performed with the new APIC code. However, an SMP kernel will panic if there is more than one CPU and a built-in FPU is not found. - PCI interrupts are now properly routed when using APICs to route interrupts, so remove the hack to psuedo-route interrupts when the intpin register was read. - The apic.h header was moved to apicreg.h and a new apicvar.h header that declares the APIs used by the new APIC code was added.
* Lower the priority of the legacy host to pci bridge driver so that otherjhb2003-10-311-1/+1
| | | | non-ACPI host-bridge drivers can preempt this driver.
* Change all SYSCTLS which are readonly and have a related TUNABLEsilby2003-10-212-2/+2
| | | | | from CTLFLAG_RD to CTLFLAG_RDTUN so that sysctl(8) can provide more useful error messages.
* We represent PCI intpin's two different ways. One is the way that thejhb2003-09-102-2/+2
| | | | | | | | | | intpin register is expressed in hardware where 0 means none, 1 means INTA, 2 INTB, etc. The other way is commonly used in loops where 0 means INTA, 1 means INTB, etc. The matchpin argument to pci_cfgintr_search() is supposed to be the first form, but we passsed in a loop index of the second. This fix adds one to the loop index to convert to the first form. Reported by: Pavlin Radoslavov <pavlin@icir.org>
* - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.jhb2003-08-281-3/+3
| | | | | | | | | | | - Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds the header type. - Replace several magic numbers with appropriate constants for the header type register and a couple of PCI_FUNCMAX. - Merge to amd64 the fix to the i386 bridge code to skip devices with unknown header types. Requested by: imp (1, 2)
* Prefer new location of pci include files (which have only been in theimp2003-08-221-3/+3
| | | | | tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
* PC98 uses different mask of IRQ.nyan2003-08-022-4/+16
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* The MI code was modified to filter the devices based on its headerimp2003-08-011-0/+8
| | | | | | | | | | | | type. We know about header types 0, 1 and 2. Ignore the rest in the MD i386 code when we're looking for bridges. You cannot look at the vendor tag. And if you don't you certainly can't look at function > 0 if the device isn't there. The new soekris boards' GEODE cpu has issues with the old way. This is reported to have fixed it. MFC After: 2 days
* Add hw.pci.irq_override_mask, which is a mask of interrupts that areimp2003-08-012-0/+28
| | | | | | | considered to be good to try when it otherwise has no clue about which interrupts to try. This is a band-aide and we really should try to balance the IRQs that we arbitrarily pick, but it should help some people that would otherwise get bad IRQs.
* - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for ajhb2003-06-061-56/+50
| | | | | | | | | | | | | while after the legacy device was added since this driver hangs from legacy and not nexus. - Make several methods non-static so they can be reused in a mptable host -> pci bridge driver that will be added at a later date. - Let legacy_pcib() use pcibios_pcib_route_interrupt() directly instead of wrapping it in a private function. Originally, I thought I was going to have the nexus_pcib() driver make a runtime APIC vs. 8259A check and call the appropriate routing method (MPTable vs. PIR) that way, but it ended up being cleaner to make nexus_pcib() just work with PIR and have a separate host -> pci bridge driver for the mptable/apic case.
* Use the secondary bus number instead of the number of the bus the PCI-PCIjhb2003-06-061-1/+5
| | | | | | bridge lives on (i.e., the parent bus) when probing the PIR table for a bus. This could cause the PCIBIOS PCI-PCI bridge driver to bogusly attach to bridges that weren't in the PIR but whose parent bus was in the PIR.
* Use __FBSDID().obrien2003-06-023-9/+9
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* Remove unused variable.phk2003-05-311-2/+1
| | | | Found by: FlexeLint
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-183-276/+56
| | | | | | | | | | | | | | #if'ed out for a while. Complete the deed and tidy up some other bits. We need to be able to call this stuff from outer edges of interrupt handlers for devices that have the ISR bits in pci config space. Making the bios code mpsafe was just too hairy. We had also stubbed it out some time ago due to there simply being too much brokenness in too many systems. This adds a leaf lock so that it is safe to use pci_read_config() and pci_write_config() from interrupt handlers. We still will use pcibios to do interrupt routing if there is no acpi.. [yes, I tested this] Briefly glanced at by: imp
* Outdent the string rather than use concatenation.phk2002-12-231-2/+2
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* MFp4:imp2002-11-142-2/+2
| | | | | o Fix small style nit. This was supposed to be part of the last batch of style fixes, but somehow didn't get merged.
* Recognize the Serverworks CIOB30 host to pci bridge.peter2002-11-131-0/+5
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* MFp4:imp2002-11-022-20/+68
| | | | | | | | | | | | | | | o It turns out that we always need to try to route the interrupts for the case where the $PIR tells us there can be only one. Some machines require this, while others fail when we try to do this (bogusly, imho). Since we have no apriori way of knowing which is which, we always try to do the routing and hope for the best if things fail. o Add some additional comments that state the obvious, but amplify it in non-obvious ways (judging from the questions I've gotten). This should un-break older laptops that still have to use PCIBIOS to route interrupts. Tested by: sam
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-022-20/+22
| | | | | | | Use exact width types, since this is a MD file and won't be used elsewhere. Fix a couple of resulting printf breakages Bug found by: phk using Flexlint
* Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread().phk2002-10-201-0/+2
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* "id" is never going to be -1 when it is unsigned.phk2002-10-201-2/+0
| | | | Spotted by: FlexeLint
* Use the global pcib devclass instead of our own static copy.jhb2002-10-161-2/+0
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* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-072-14/+24
| | | | | | | | | | | there are some strange machines that seem to need this. o delete bogus comment. o don't use the the bios for read/writing config space. They interact badly with SMP and being called from ISR. This brings -current in line with -stable. # make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we # need to go back in a hurry.
* Add 2 Ids for new ServerWorks host to PCI bridge chipset.iwasaki2002-10-021-0/+8
| | | | | | | | | These are still unknown name but these are working as well as the other ServerWorks chipset. Description strings should be corrected when the chipsets are known. MFC after: 1 week
* Don't call function in return() for a void function.phk2002-09-282-6/+10
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* Now that we only probe host-PCI bridges once, we no longer have to check tojhb2002-09-231-10/+0
| | | | see if we have been probed before by checking for a pciX bus device.
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-232-2/+8
| | | | if (bootverbose).
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