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* Make a bunch of malloc types static.phk2005-02-101-1/+1
* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-063-3/+3
* Remove a stray critical_exit().scottl2004-12-131-1/+0
* Expand the scope of the critical section in the PCIe read and write methodsscottl2004-12-101-4/+14
* Due to a significant addition of code, add my copyright to this file. Alsoscottl2004-12-061-0/+1
* Add support for the memory-mapped PCI Express configuration mechanism. Thisscottl2004-12-061-8/+211
* Add TUNABLE_LONG and TUNABLE_ULONG, and use the latter for thedes2004-10-311-4/+3
* Whitespace cleanupdes2004-10-311-8/+8
* Make the lower range of the memory area 0x80000000 again. Alsoimp2004-10-111-1/+15
* Add missing 'static'imp2004-10-061-2/+1
* For legacy PCI bridges, limit memory allocation to the top 32MB ofimp2004-10-061-4/+24
* Consistently use __inline instead of __inline__ as the former is an empty macrostefanf2004-07-041-1/+1
* Trim a few things from the dmesg output and stick them under bootverbose tojhb2004-07-012-4/+5
* Remove atdevbase and replace it's remaining uses with direct references tojhb2004-06-101-0/+1
* Allow the pir0 device add to fail since pir0 may already exist. This shouldjhb2004-06-011-2/+2
* Add some missing <sys/module.h> includes which are masked by thephk2004-05-302-0/+2
* - Create a pir0 psuedo device as a child of legacy0 if we attach a legacyjhb2004-05-042-8/+125
* Make the legacy_pcib_attach() function static.jhb2004-05-031-1/+1
* Don't call the BIOS to route a link that has already been routed by thejhb2004-04-161-2/+3
* Add back an include to fix the build for the CPU_ELAN case.jhb2004-02-191-0/+3
* Switch to using the new $PIR interrupt routing code and remove the oldjhb2004-02-182-434/+17
* Rework the $PIR (aka PCIBIOS) PCI interrupt routing code and split it offjhb2004-02-181-609/+445
* Replace an outb() during the test for configuration mechanism #1 with ajhb2003-12-312-2/+2
* New APIC support code:jhb2003-11-032-98/+4
* Lower the priority of the legacy host to pci bridge driver so that otherjhb2003-10-311-1/+1
* Change all SYSCTLS which are readonly and have a related TUNABLEsilby2003-10-212-2/+2
* We represent PCI intpin's two different ways. One is the way that thejhb2003-09-102-2/+2
* - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.jhb2003-08-281-3/+3
* Prefer new location of pci include files (which have only been in theimp2003-08-221-3/+3
* PC98 uses different mask of IRQ.nyan2003-08-022-4/+16
* The MI code was modified to filter the devices based on its headerimp2003-08-011-0/+8
* Add hw.pci.irq_override_mask, which is a mask of interrupts that areimp2003-08-012-0/+28
* - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for ajhb2003-06-061-56/+50
* Use the secondary bus number instead of the number of the bus the PCI-PCIjhb2003-06-061-1/+5
* Use __FBSDID().obrien2003-06-023-9/+9
* Remove unused variable.phk2003-05-311-2/+1
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-183-276/+56
* Outdent the string rather than use concatenation.phk2002-12-231-2/+2
* MFp4:imp2002-11-142-2/+2
* Recognize the Serverworks CIOB30 host to pci bridge.peter2002-11-131-0/+5
* MFp4:imp2002-11-022-20/+68
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-022-20/+22
* Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread().phk2002-10-201-0/+2
* "id" is never going to be -1 when it is unsigned.phk2002-10-201-2/+0
* Use the global pcib devclass instead of our own static copy.jhb2002-10-161-2/+0
* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-072-14/+24
* Add 2 Ids for new ServerWorks host to PCI bridge chipset.iwasaki2002-10-021-0/+8
* Don't call function in return() for a void function.phk2002-09-282-6/+10
* Now that we only probe host-PCI bridges once, we no longer have to check tojhb2002-09-231-10/+0
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-232-2/+8
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